Semiconductor Memory Bank Data Position Shifting for Error Correction
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Solution Overview
Problem
The increasing number of failed memory cells in semiconductor devices due to high integration levels leads to reduced production yield and difficulty in ensuring large memory capacity, necessitating effective error correction mechanisms.
Innovation Solution
A semiconductor system that shifts storage positions of data and error information based on the number of times specific address signals are inputted, using control signals and shifting signals to generate internal data, thereby enhancing error correction and storage reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration levels are used to increase memory capacity, then memory capacity is improved, but the number of failed memory cells increases
Solution Approach 1:
The memory array is divided into multiple banks, and each bank is further divided into multiple pages. This segmentation allows the system to isolate and manage failed memory cells at the page level rather than affecting the entire memory array, thereby maintaining high memory capacity while improving reliability through localized error handling.
Solution Approach 2:
An error correction code (ECC) circuit is introduced as an intermediary between the memory array and the output. The ECC circuit detects and corrects errors in data read from the memory array, acting as a mediator that prevents failed memory cells from compromising overall system reliability while maintaining full memory capacity.
2Reliability
If ECC circuits are employed to correct data errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The ECC functionality is segmented and distributed across different components: error detection is performed at the page level within each bank, and correction is handled by dedicated ECC circuits. This segmentation reduces the complexity of any single ECC unit while maintaining overall system reliability through distributed error handling.
Solution Approach 2:
Error correction codes are calculated and stored alongside data during the write operation, before any potential errors occur. This preliminary action allows errors to be detected and corrected during read operations without requiring complex real-time analysis, thereby reducing the complexity of the error correction mechanism.
3Loss of information
If write operations are performed frequently to update data, then data freshness is improved, but the number of failed memory cells increases
Solution Approach 1:
The memory array is organized into multiple banks and pages, allowing write operations to be distributed across different segments. This segmentation prevents any single memory cell from being overwritten excessively, as data can be rotated across different pages and banks, thereby reducing wear on individual cells while maintaining data freshness.
Solution Approach 2:
The system implements periodic wear leveling by cyclically rotating data between different pages and banks. This periodic action ensures that write operations are distributed evenly across all memory segments over time, preventing any single cell from degrading due to excessive writes while maintaining up-to-date data availability.
Data Source
AI summary
A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.