Semiconductor Memory Bank Delay Control for Read Time Synchronization
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Solution Overview
Problem
Semiconductor memory devices experience a data read time difference between memory banks due to varying distances from the data control block, leading to reduced operation time margins for buffering and providing global read data.
Innovation Solution
The semiconductor memory device incorporates a data control block that generates read confirmation signals for each memory bank, with command and auxiliary wirings that adjust delay times to synchronize data read operations across memory banks, ensuring consistent data read times by introducing delay control times and auxiliary wirings to manage signal arrival and data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory banks are positioned at different distances from the data control block, then the memory device can accommodate more memory banks, but the data read time difference between memory banks increases
Solution Approach 1:
The patent applies parameter changes by introducing different delay control times for different memory banks. Specifically, the first memory bank has a first delay control time and the second memory bank has a second delay control time that is shorter than the first. This compensates for the distance difference and equalizes the data read time across all memory banks.
Solution Approach 2:
The patent implements preliminary action by pre-calculating and pre-setting different delay control times for each memory bank based on their respective distances from the data control block. The delay control parts are configured in advance to compensate for signal transmission time differences, ensuring synchronized data read operations before actual read commands are executed.
2Loss of time
If delay control times are adjusted for different memory banks, then data read time difference is reduced, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory device into multiple independent memory banks, each with its own delay control part. The first delay control part is associated with the first memory bank and the second delay control part is associated with the second memory bank. This modular approach allows independent optimization of each bank's timing without affecting others.
Solution Approach 2:
The patent implements local quality by providing customized delay control for each memory bank based on its specific distance from the data control block. Each delay control part is locally optimized for its corresponding memory bank, with the first delay control part having a first delay control time and the second delay control part having a second delay control time tailored to their respective positions.
Data Source
AI summary
Disclosed herein is a semiconductor memory device for reducing data read time difference between memory banks. In the semiconductor memory device of the disclosure, each of the memory banks has the delay control time controlled based on the distance from data control block or receives the signal according to the read command. Accordingly, the data read time difference is reduced in the semiconductor memory device, and the operation time margin of the data control block is improved.