Memory Bank Erasure Logic for Protected Multi-Context Operation
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Solution Overview
Problem
Existing memory controller circuits in multi-context environments face challenges in efficiently and securely erasing memory banks while ensuring immutability and security features, particularly in scenarios where context assignments are dynamically changing at runtime.
Innovation Solution
Implementing an erase logic circuit that combines baseline and context-specific immutable sector configuration data to manage memory bank erasure operations, allowing contexts to request and initiate bank-level erasure while ensuring only permitted sectors are erased, and utilizing hardware logic to generate updated ISC data efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor core waits for the erase logic circuit to complete all processing before allowing other contexts to run, then the erase operation can be completed accurately with proper permission checking, but the system productivity and context switching efficiency deteriorate
Solution Approach 1:
The erase logic circuit performs preliminary actions by pre-determining permissions for each address range and pre-identifying immutable address ranges before the actual erase operation begins. This preparation work is completed in advance, allowing the processor core to switch to other contexts without waiting for the complete erase process, thus maintaining both accuracy and productivity
Solution Approach 2:
The erase logic circuit acts as an intermediary component between the processor core and the memory controller circuit. It handles the complex permission checking and address range determination independently, then communicates only the essential erase parameters to the memory controller. This mediation allows the processor core to remain responsive and switch contexts while the erase operation proceeds in the background
2Reliability
If the system performs comprehensive permission checking for all address ranges before erasure, then security and data protection are improved, but the device complexity and processing overhead increase
Solution Approach 1:
The memory address space is segmented into multiple address ranges, each with its own permission attributes. The erase logic circuit processes these segments independently, determining permissions for each range separately. This segmentation simplifies the overall complexity by breaking down the large task of checking all addresses into smaller, manageable units that can be processed efficiently
Solution Approach 2:
Different address ranges are assigned different permission qualities based on their specific security requirements. Some ranges may be fully erasable, others partially protected, and some completely immutable. This local differentiation allows the system to apply appropriate security measures only where needed, rather than uniformly across the entire memory space, thus reducing overall complexity while maintaining security
3Reliability
If the erase operation is performed on the entire memory bank, then the erasure completeness is improved, but the time required for the operation and data loss increase
Solution Approach 1:
The system performs partial erasure actions only on the specific address ranges that require erasure based on permission checks and immutability attributes. Rather than erasing the entire memory bank unnecessarily, the erase logic circuit precisely targets only the permitted ranges, completing the necessary erasure work faster while preserving data that should not be erased
Solution Approach 2:
The erase logic circuit performs preliminary identification of immutable address ranges and determination of erasable ranges before the actual erase operation. This pre-processing ensures that when the erase operation commences, it can proceed immediately and efficiently on the correctly identified ranges without unnecessary delays or re-evaluation, thus reducing total operation time while maintaining completeness
Data Source
AI summary
A system includes a memory having a memory bank, a memory controller circuit, and an erase logic circuit. A context, running on a processor core, may determine to erase (reinitialize) the memory bank. The context may transmit an indication of the memory bank to be erased to the erase logic circuit. The erase logic circuit may determine immutable address ranges as well as permissions data and may combine data regarding the immutable address ranges with the permissions data. The erase logic circuit may then transmit bits to the memory controller circuit to identify address ranges to be protected from a bank erase operation. The context may then issue a bank erase command to the memory controller, which may erase the memory bank consistent with the bits transmitted from the erase logic circuit.