Memory Bank Error Check and Refresh Segmentation
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Solution Overview
Problem
As semiconductor memory devices increase in capacity, it becomes challenging to fabricate memory devices without defective memory cells, leading to the need for repair methods using redundant cells and error correction circuits.
Innovation Solution
A method and system for operating a memory that includes performing an error check operation on a selected row and column of one memory bank and a refresh operation on other memory banks in response to a predetermined command, utilizing a control signal generating circuit, error correction circuit, and memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error check operation is performed on all memory banks, then error detection capability is improved, but operation time increases
Solution Approach 1:
The memory system is divided into multiple memory banks, and the error check operation is segmented to be performed on only one selected memory bank at a time, while other banks undergo refresh operations. This segmentation allows parallel processing of error checking and refresh operations across different banks, reducing total operation time while maintaining error detection capability.
Solution Approach 2:
The error check operation is performed periodically on selected memory banks in a round-robin fashion, rather than continuously on all banks. This periodic approach ensures that each bank is checked for errors at regular intervals while allowing other banks to be refreshed in between, balancing error detection with operational efficiency.
2Stability of the object's composition
If refresh operation is performed on all memory banks, then data retention is improved, but operation time increases
Solution Approach 1:
The refresh operation is segmented across multiple memory banks, with only one bank selected for error checking at a time while others receive refresh operations. This ensures that data retention is maintained across all banks through periodic refreshes without requiring all banks to be refreshed simultaneously, reducing total operation time.
3Reliability
If redundant memory cells are added for repair, then reliability is improved, but device complexity increases
Solution Approach 1:
An error correction circuit is introduced as an intermediary component that works in conjunction with the memory banks. This circuit performs error detection and correction operations on data read from memory cells, providing a systematic approach to handling defective cells without requiring complex physical restructuring of the memory array itself.
Data Source
AI summary
A method for operating a memory includes: receiving a predetermined command; performing an error check operation on a selected row and selected columns of one memory bank among a plurality of memory banks in response to the predetermined command; and performing a refresh operation on a selected row of each of the other memory banks among the memory banks in response to the predetermined command.