Memory Bank Data Transfer via Internal Data Bus
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Solution Overview
Problem
Existing memory systems face inefficiencies in data transfer between banks, leading to increased processing time and power consumption due to reliance on external data buses, which can be improved by enabling internal data bus transfers within memory devices.
Innovation Solution
Implementing an internal data bus within memory devices to facilitate direct data transfer between banks without using external data buses, utilizing sensing circuitry to perform operations and reduce reliance on external processing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data transfer between banks uses external data buses, then device complexity is reduced, but processing time increases and power consumption increases
Solution Approach 1:
The patent introduces a new spatial dimension for data transfer by implementing an internal data bus within the memory device that enables direct bank-to-bank communication. This internal pathway operates in parallel to the external bus system, creating a multi-dimensional data transfer architecture where data can move internally without traversing external connectors and traces, thereby reducing processing time while maintaining structural simplicity
2Device complexity
If data transfer between banks uses external data buses, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The patent creates an internal data transfer pathway that operates within the memory device footprint, eliminating the need for data to traverse external bus connectors and PCB traces. This internal dimension reduces the physical distance data must travel and the number of interface stages, thereby reducing power consumption while keeping the overall device structure relatively simple
3Ease of manufacture
If processing resources are external to memory array, then ease of manufacture is improved, but processing performance decreases
Solution Approach 1:
The patent merges the processing resources with the memory array by integrating the internal data bus and control logic directly into the memory device fabric. This consolidation allows processing operations to occur in close proximity to data storage, reducing access latency and improving processing performance while maintaining manufacturing simplicity through standard integrated circuit fabrication processes
Data Source
AI summary
The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.