Semiconductor Memory Bank Layout for Uniform Power
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Solution Overview
Problem
Semiconductor memory devices with multiple banks face challenges in maintaining uniform power consumption and alternating current (AC) characteristics due to varying lengths of data transfer paths and power supply paths, which affect access speed and cycle time.
Innovation Solution
The semiconductor memory device is configured with multiple banks and a peripheral circuit that maintains constant lengths of data transfer paths or power supply paths between activated banks, allowing simultaneous activation of banks across chips to ensure uniform power consumption and improved AC characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple banks are activated simultaneously to improve access speed, then productivity is improved, but power consumption becomes non-uniform due to varying path lengths
Solution Approach 1:
The patent applies asymmetry by intentionally designing different physical layouts for banks within the same bank group, where banks are positioned at different distances from the peripheral circuit. This asymmetric arrangement compensates for the varying path lengths through strategic bank placement, ensuring that the sum of data line lengths and power supply path lengths remains substantially equal across different bank activation scenarios, thereby maintaining uniform power consumption while enabling simultaneous multi-bank activation for improved access speed.
2Volume of stationary object
If banks are arranged with varying data line lengths to increase capacity, then volume is improved, but AC characteristics deteriorate due to data skew
Solution Approach 1:
The patent applies equipotentiality by arranging banks within the same bank group such that the sum of data line lengths from the peripheral circuit to activated banks is substantially equal, regardless of which specific banks are activated. This is achieved through symmetric positioning of banks relative to the peripheral circuit, ensuring that data signals experience equal propagation delays. Additionally, power supply paths are designed with equal lengths to maintain uniform power delivery, thereby eliminating data skew and improving AC characteristics while supporting increased memory capacity through multiple bank groups.
3Productivity
If the number of banks is increased to improve productivity, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory device into multiple bank groups, with each bank group containing multiple banks that share common data lines and power supply paths. This hierarchical segmentation allows simultaneous activation of banks across different bank groups without requiring complex independent routing for each bank. The shared resources reduce the overall complexity of data line and power supply network management, enabling increased bank count for improved productivity while maintaining manageable device complexity through modular organization.
Data Source
AI summary
A semiconductor memory device includes a plurality of banks; a peripheral circuit configured to send data to and receive data from the plurality of banks; and data lines configured to connect the plurality of banks and the peripheral circuit, wherein the plurality of banks are disposed such that a sum of lengths of data transfer paths of the data lines connecting the peripheral circuit and at least two banks, among the plurality of banks, activated at a same time is uniformly maintained.