Memory Bank Multi-Word Line Activation for Bandwidth
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Solution Overview
Problem
Current memory devices face challenges in increasing bandwidth due to limitations in activating multiple word lines within a single memory bank, which restricts their operating speed and efficiency.
Innovation Solution
The proposed solution involves a memory device architecture that allows simultaneous activation of two or more word lines in a single memory bank, along with sequential access to connected memory cells, and efficient management of other word lines through active or refresh operations, enabling dual modes of operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single word line is activated in a memory bank, then the memory device operates with conventional control simplicity, but the bandwidth is limited and cannot be increased efficiently
Solution Approach 1:
The memory bank is segmented into multiple memory blocks (first memory block, second memory block), each with its own word lines. This segmentation allows independent activation and access of word lines from different blocks simultaneously, enabling multi-word line operations that increase bandwidth without overwhelming the control logic.
Solution Approach 2:
The patent introduces a new dimension of operation by enabling simultaneous activation of word lines from different memory blocks within the same bank. Traditionally, only one word line per bank could be active at a time; this invention adds the dimension of parallel block selection, allowing WL0 from block0 and WL1 from block1 to be active concurrently, thus multiplying the effective bandwidth.
2Productivity
If multiple memory banks are accessed alternately, then the bandwidth can be increased through parallel operations, but the row address strobe to row address strobe delay (tRRD) limits the consecutive access speed
Solution Approach 1:
The patent merges the functionality of multiple memory banks by enabling a single memory bank to perform multi-word line operations. Instead of requiring alternating access to bank0 and bank1, the system can activate word lines from different blocks within bank0 simultaneously, effectively merging the parallel access capability of multiple banks into a single bank operation, thereby reducing the tRRD delay constraint.
Solution Approach 2:
The patent implements preliminary action by pre-activating multiple word lines from different memory blocks within the same bank before data access operations. This allows the memory system to prepare multiple data paths in advance, reducing the effective delay between consecutive access operations and improving the sustained bandwidth without being bottlenecked by tRRD constraints.
3Productivity
If word lines in unselected memory blocks remain inactive, then the control logic remains simple, but the memory device cannot achieve efficient utilization of all memory resources
Solution Approach 1:
The memory bank is designed with universal functionality to handle both single-word line and multi-word line operations. The same memory bank structure and control logic can operate in conventional mode (single word line active) or enhanced mode (multiple word lines from different blocks active simultaneously), providing multi-functionality that improves memory utilization without requiring separate dedicated circuits for each operation mode.
Data Source
AI summary
A memory device includes a first memory bank comprising first and second memory blocks; a second memory bank comprising third and fourth memory blocks; and a bank selection unit suitable for selecting a memory bank corresponding to a bank address among the first and the second memory banks when an active command is applied, wherein the selected memory bank performs row access on a word line of an unselected memory block, while activating a word line of a memory block that is selected by a block address among memory blocks of the selected memory bank.