Memory Bank Polling Allocation for Reduced Controller Circuit Scale
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Solution Overview
Problem
Existing memory systems face inefficiencies in managing a large number of memory banks due to a fixed one-to-one association between polling circuits and banks, leading to redundant or underutilized polling circuits, which affects performance and circuit scale.
Innovation Solution
A memory system design that dynamically allocates banks to polling circuits, allowing equivalent control even when the number of banks exceeds the number of polling circuits, using a bank interleaving method to optimize performance without increasing circuit scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed one-to-one association between polling circuits and banks is used, then each bank can be monitored independently, but the circuit scale increases and redundancy occurs when the number of banks exceeds the number of polling circuits
Solution Approach 1:
Each polling circuit is designed to monitor multiple banks sequentially rather than being dedicated to a single bank. The polling circuit can be dynamically assigned to different banks based on operational needs, allowing one polling circuit to serve multiple banks and thereby reducing the total number of polling circuits required while maintaining reliable monitoring coverage.
Solution Approach 2:
The association between polling circuits and banks is made dynamic rather than static. The memory controller can reassign polling circuits to different banks in real-time based on the operational state of banks and polling circuits, optimizing resource utilization and reducing redundancy without compromising monitoring reliability.
2Productivity
If the number of polling circuits is increased to match the number of banks, then monitoring performance improves, but circuit scale and cost increase
Solution Approach 1:
Multiple bank monitoring functions are merged into a single polling circuit through time-division multiplexing. The polling circuit sequentially monitors multiple banks by switching between them, combining the monitoring capability for multiple banks into one circuit unit, thereby improving monitoring performance without proportionally increasing circuit scale.
Solution Approach 2:
The polling circuit performs periodic monitoring of banks in a cyclic manner, systematically checking each bank's status at regular intervals. This periodic action ensures that all banks are monitored comprehensively over time, maintaining high monitoring performance while using fewer polling circuits through efficient time utilization.
3Productivity
If bank interleaving method is used to operate memory elements in parallel, then performance improves, but efficient management becomes difficult without dynamic allocation
Solution Approach 1:
The memory controller implements feedback mechanisms to track the operational status of each bank and the availability of polling circuits. Based on this feedback information, the controller dynamically adjusts the assignment of polling circuits to banks, ensuring optimal management of parallel operations and maintaining ease of operation even as the system scales.
Solution Approach 2:
The system pre-configures polling circuit assignments and bank interleaving patterns to optimize parallel operation performance. By establishing these assignments in advance based on expected operational patterns, the system achieves high performance while maintaining manageable complexity through predetermined efficient allocation strategies.
Data Source
AI summary
A memory system includes a memory controller and a first number of memory elements connected to the memory controller via one or more channels. The memory controller includes a second number of polling circuits and a first processor. Each polling circuit receives designation of one memory element out of the first number of memory elements and executes a polling operation. The polling operation is an operation to repeat an inquiry to the designated memory element until detecting that a status of the designated memory element is a ready status. The first processor selects a polling circuit that is not executing the polling operation among the second number of polling circuits. The first processor designates, for the selected polling circuit, one memory element out of the first number of memory elements and causes the selected polling circuit to execute the polling operation on the designated one memory element.