Memory Banks With Pre-Read Encoding for Faster Unaligned Writes
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Solution Overview
Problem
Unaligned writes in memory operations require additional clock cycles due to an additional read operation, reducing overall memory efficiency, especially in scenarios where unaligned writes occur frequently.
Innovation Solution
Implement a memory operation method using a read-write parallel protocol with multiple memory banks, where data is written to a first memory bank in a current clock cycle and pre-read data from a second memory bank in the same cycle for encoding in the next cycle, allowing simultaneous read and write operations on different banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If unaligned write operations are performed in memory, then data can be written to non-aligned addresses, but additional clock cycles are required due to extra read operations
Solution Approach 1:
The patent implements a pre-read mechanism where data is read from memory in advance before the write operation is actually needed. The read controller pre-reads data from the second memory bank corresponding to the next logical address during the current clock cycle, so that when the unaligned write occurs in the next clock cycle, the data is already available in the buffer, eliminating the need for an additional clock cycle.
Solution Approach 2:
The patent divides the memory system into multiple independent memory banks (first memory bank and second memory bank) that can operate independently and in parallel. This segmentation allows the read and write operations to be performed on different banks simultaneously, resolving the contradiction between handling unaligned writes and maintaining write speed.
2Productivity
If parallel read-write protocol is used with multiple memory banks, then read and write efficiency can be improved, but unaligned writes still require additional clock cycles
Solution Approach 1:
The patent implements a pre-read mechanism where data is read from memory in advance before the write operation is actually needed. The read controller pre-reads data from the second memory bank corresponding to the next logical address during the current clock cycle, so that when the unaligned write occurs in the next clock cycle, the data is already available in the buffer, eliminating the need for an additional clock cycle.
Solution Approach 2:
The patent ensures continuous useful action by overlapping the read and write operations in time. The pre-read operation occurs during the current clock cycle while the write operation is prepared, and the encoded data is written in the next clock cycle without idle waiting time, maximizing the utilization of the parallel protocol capabilities.
3Productivity
If pre-read operation is implemented for unaligned writes, then write speed can be improved, but read-write conflicts may occur on the same memory bank
Solution Approach 1:
The patent divides the memory system into multiple independent memory banks (first memory bank and second memory bank) that can operate independently and in parallel. This segmentation allows the read and write operations to be performed on different banks simultaneously, resolving the contradiction between handling unaligned writes and maintaining write speed.
Solution Approach 2:
The patent introduces a write controller as an intermediary that coordinates between the read controller and the memory banks. The write controller receives the pre-read data, performs encoding operations, and manages the write operation timing, ensuring that read and write operations on the same memory bank are properly sequenced and conflicts are avoided.
Data Source
AI summary
Disclosed are a memory operating method, memory and electronic device. The memory follows a read-write parallel protocol and includes a plurality of memory banks, and the method comprises: writing data to a specified location of the first memory bank corresponding to a current logical address, and pre-reading original data in a specified location of the second memory bank corresponding to a next logical address in a current clock cycle; encoding the pre-read original data and data to be written next, when an instruction to encode based on the pre-read original data in a next clock cycle is obtained; and writing the encoded data to the specified location of the second memory bank in the next clock cycle. By pre-reading the original data corresponding to the incremental address in the current clock cycle, the present disclosure can accelerate an encoding operation that may occur next.