Memory Bank Processor Layout for Reduced Command Transfer Latency
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Solution Overview
Problem
Current memory devices face inefficiencies due to external control circuitry, leading to bandwidth bottlenecks and performance degradation, especially in IoT applications where multiple memory devices ingest and transfer data to a host, resulting in increased command transfer times and power consumption.
Innovation Solution
Incorporating a system processor resident on the memory device to control memory operations locally, reducing the need for external command transfers and enabling processing-in-memory (PIM) operations, thereby decreasing command latency and bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory devices use external control circuitry to manage operations, then device complexity is reduced and ease of manufacture is improved, but command transfer times increase and processing performance degrades
Solution Approach 1:
The memory device incorporates a system processor resident on the memory device itself, enabling the memory device to autonomously control its own operations without requiring external control circuitry. This self-service approach allows the memory device to execute commands locally, eliminating command transfer delays while maintaining manufacturing simplicity through integrated design
2Productivity
If multiple memory devices transfer data to a host, then data processing capability is improved, but bandwidth bottlenecks increase and performance degradation occurs
Solution Approach 1:
The system processor is divided into specialized functional units including an arithmetic logic unit, floating point unit, and combinatorial logic block. This segmentation allows different types of operations to be executed in parallel across multiple functional units, increasing data processing capability while distributing bandwidth consumption across specialized pathways rather than saturating a single external interface
Solution Approach 2:
The patent transitions from traditional external processing to internal processing-in-memory by adding a system processor resident on the memory device. This dimensional shift moves computation from the external host dimension to the internal memory dimension, enabling data processing to occur where data resides, thereby reducing bandwidth consumption on external interfaces while maintaining high productivity
3Device complexity
If processing operations are performed externally to the memory array, then device complexity is reduced, but processing performance and power efficiency deteriorate
Solution Approach 1:
The patent merges the system processor directly with the memory device by integrating it into the memory array structure. The processor is coupled to the memory array through local interconnects, combining storage and processing functions in a single integrated device. This merging increases processing performance by eliminating data transfer between separate components while the modular integration approach maintains manageable device complexity
Data Source
AI summary
An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.