Memory Bank Mapping with Rank Bit Grouping for Higher Bandwidth
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Solution Overview
Problem
Emerging memory technologies, such as 3D cross-point memory, suffer from slower page cycle times compared to DRAM and FeRAM, leading to performance bottlenecks and increased complexity or cost when implementing higher bank counts in memory sub-systems.
Innovation Solution
Implementing mapping circuitry to group banks together, allowing them to appear as a single bank to the controller, and setting rank-to-rank delay to zero, thereby optimizing single rank architectures without increasing controller complexity or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bank count is increased to achieve performance threshold, then the bandwidth is improved, but the controller complexity increases
Solution Approach 1:
The patent segments the bank addressing space by introducing a rank bit that divides banks into multiple ranks. Instead of having a single controller manage all banks directly, the controller manages multiple ranks, each with fewer banks. This segmentation reduces the complexity of bank management within each rank while maintaining the ability to access a large total number of banks across all ranks, thereby improving bandwidth without proportionally increasing controller complexity.
Solution Approach 2:
The patent adds a new dimension to the address space by introducing the rank bit, transforming the traditional single-dimension bank addressing into a multi-dimensional address structure. This allows the system to organize banks in a hierarchical manner (ranks containing banks), effectively increasing the addressable bank count without requiring the controller to directly manage every individual bank, thus reducing controller complexity while maintaining high bandwidth.
2Speed
If the bank count is increased to overcome slow page cycle time, then the performance is improved, but the controller size increases
Solution Approach 1:
The controller is segmented into multiple rank controllers, each managing a subset of banks. This segmentation allows the overall controller to handle a large number of banks without each individual controller unit becoming overly complex. By dividing the bank management task across multiple smaller rank controllers, the patent reduces the size and complexity of each controller unit while maintaining the ability to manage a large total bank count for improved performance.
Solution Approach 2:
The patent implements partial ranking, where not all banks need to be accessed simultaneously through complex coordination. By organizing banks into ranks and allowing independent access to different ranks, the system achieves high performance without requiring the full complexity of managing all banks as a single unit. This partial action approach reduces controller size while maintaining the performance benefits of high bank counts.
3Productivity
If the bank count is increased to achieve optimal performance, then the bandwidth is improved, but the cost increases
Solution Approach 1:
The controller architecture is segmented into multiple identical or similar rank controller units. This modular segmentation allows for standardized design and manufacturing of each rank controller, reducing development costs and enabling easier production scaling. By using repeated modular units rather than a single complex custom controller, the patent reduces the overall cost while maintaining the ability to manage high bank counts for optimal bandwidth performance.
Data Source
AI summary
Mapping addresses to banks can include receiving a plurality of row bits, a plurality of column bits, and a plurality of bank bits and generating a rank bit from a bank bit from the plurality of bank bits. Updated bank bits can be generated by removing the bank bit from the plurality of bank bits. The plurality of row bits, the plurality of column bits, the rank bit, and the updated bank bits can be provided to the controller to access a plurality of banks of the memory device.