Semiconductor Memory Bank Group Refresh Control
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Solution Overview
Problem
Conventional semiconductor memory devices require multiple refresh control units due to increased integration, leading to an increased area for the refresh logic circuit, which is inefficient and prone to word line disturbance affecting memory cell data.
Innovation Solution
The semiconductor memory device is designed with a bank group structure where each bank group includes a first, second, third, and fourth bank disposed along different directions, with a shared refresh control unit between row control regions, reducing the number of refresh control units and area required for the refresh logic circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple refresh control units are disposed in each bank group to handle increased integration, then the refresh control capability is improved, but the area of the refresh logic circuit is increased
Solution Approach 1:
The patent merges the refresh control functionality into a single shared refresh control unit that serves multiple bank groups. Instead of having separate refresh control units for each bank group, one refresh control unit is designed to control refresh operations across all bank groups, thereby reducing the total area of refresh logic circuits while maintaining adequate refresh control capability.
Solution Approach 2:
The refresh control unit is designed with multi-functionality to handle refresh operations for multiple bank groups simultaneously. It can selectively activate word lines in different bank groups based on refresh requirements, making a single unit capable of performing the work that would otherwise require multiple dedicated units.
2Quantity of substance
If the interval among word lines is reduced to increase integration, then the memory cell density is improved, but the coupling effect among adjacent word lines is increased causing data deterioration
Solution Approach 1:
The patent implements preliminary anti-action by performing refresh operations on memory cells in adjacent bank groups before the coupling effect can cause significant data deterioration. The refresh control unit detects when word lines in one bank group are activated and proactively triggers refresh operations in neighboring bank groups, counteracting the harmful coupling effect before it damages the data.
Solution Approach 2:
The patent converts the harmful coupling effect into a beneficial mechanism by using the activation of word lines in one bank group as a trigger signal to initiate refresh operations in adjacent bank groups. What would normally be a source of data deterioration (the coupling effect) becomes the basis for an automated refresh strategy that prevents data loss.
3Reliability
If multiple refresh control units are disposed to perform target row refresh operations, then the data integrity is improved, but the device complexity is increased
Solution Approach 1:
The patent combines multiple refresh control units into a single unified refresh control unit that manages target row refresh operations across all bank groups. This single unit incorporates the functionality of what would otherwise be multiple separate units, reducing device complexity while maintaining the ability to perform comprehensive refresh operations for data integrity.
Data Source
AI summary
A semiconductor memory device includes a first bank, a second bank disposed separately from the first bank along a first direction, a third bank disposed separately from the first bank along a second direction substantially perpendicular to the first direction, a fourth bank disposed separately from the second bank along the second direction and from the third bank along the first direction, a first row control region, which is disposed between the first bank and the second bank, suitable for controlling a row decoding operation of the first bank and the second bank, a second row control region, which is disposed between the third bank and the fourth bank, suitable for controlling a row decoding operation of the third bank and the fourth bank, and a refresh control unit suitable for controlling a refresh operation of the first to fourth banks.