Semiconductor Memory Bank Refresh Control Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices face difficulties in independently performing single bank and all bank refresh operations due to overlapping TRR signals, which can interfere with normal data retention and refresh processes.
Innovation Solution
A semiconductor memory device is designed with an address output control unit that generates distinct output control signals for single bank and all bank refresh operations, including a refresh pulse generation unit, address latch unit, and address output unit, allowing for independent control of row addresses and preventing signal overlap during TRR operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single TRR signal is used for both all bank refresh and single bank refresh operations, then the circuit complexity is reduced, but the single bank refresh operation cannot be independently performed due to signal overlap
Solution Approach 1:
The patent segments the single TRR signal into multiple bank-specific TRR signals (TRR0, TRR1, TRR2, TRR3) through a bank address decoder. This segmentation allows each bank to be independently targeted during single bank refresh operations while maintaining unified control during all bank refresh operations, thereby resolving the contradiction between circuit simplicity and operational independence.
Solution Approach 2:
The patent introduces a bank address decoder as an intermediary component that receives the single TRR signal and generates bank-specific TRR signals. This intermediary enables the system to maintain a simple unified control interface while achieving independent bank-level control when needed, resolving the contradiction without significantly increasing overall system complexity.
2Productivity
If the output control signal is activated during single bank refresh operation, then the refresh operation can be performed, but it overlaps with the all bank refresh operation causing interference
Solution Approach 1:
The patent segments the output control signal into multiple bank-specific output control signals (PO_FIN0, PO_FIN1, PO_FIN2, PO_FIN3), each controlling a specific bank's refresh operation. This segmentation prevents overlap between single bank refresh and all bank refresh operations by ensuring that only the intended bank's output control signal is activated at any given time, thereby maintaining both refresh performance and data retention reliability.
Solution Approach 2:
The patent applies local quality by making each output control signal bank-specific, where each signal has distinct timing and activation characteristics tailored to its corresponding bank. This allows precise control over which bank undergoes refresh operation and when, preventing harmful overlaps while maintaining efficient refresh performance for the targeted bank.
3Adaptability or versatility
If conventional single bank refresh operation is performed, then the refresh command is executed, but the TRR signal overlap prevents normal operation
Solution Approach 1:
The patent segments the refresh operation control into bank-specific components, allowing the single bank refresh operation to be executed independently without interference from all bank refresh operations. The bank address decoder and bank-specific output control signals enable flexible adaptation to different refresh scenarios while ensuring clean execution of single bank refresh commands.
Solution Approach 2:
The patent introduces dynamic control through bank-specific output control signals that are activated at different times based on the refresh operation type. During single bank refresh, only the targeted bank's output control signal is activated, while during all bank refresh, multiple signals are activated in sequence. This dynamic behavior provides operational flexibility while preventing signal overlap interference.
Data Source
AI summary
A semiconductor memory device may include: a plurality of banks suitable for performing an all bank refresh operation or single bank refresh operation; an address output control unit suitable for generating a plurality of output control signals in response to a single bank refresh pulse signal; an address latch unit suitable for outputting a target row address of a bank corresponding to an activated output control signal; and an address output unit suitable for outputting a row address adjacent to the target row address to a selected bank.