Memory Bank Refresh via Shared Address Path
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Solution Overview
Problem
In semiconductor memory devices, the shared address path for refreshing and accessing memory banks can lead to incorrect row addresses being used during refresh operations or activation operations, resulting in errors such as refreshing the wrong row or activating the wrong row, due to the overlap of refresh and access commands.
Innovation Solution
Implementing a system where bank control blocks capture and increment row addresses stored in registers to ensure that refresh operations are performed correctly while allowing simultaneous access to other memory banks, using separate counters for even and odd memory banks to maintain synchronization and prevent errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single shared address path is used for both refresh operations and access operations, then device complexity is reduced, but reliability deteriorates due to potential address conflicts between refresh and access commands
Solution Approach 1:
The patent segments the address path control by introducing separate counters for refresh operations (refresh counter) and access operations (access counter), allowing independent tracking of row addresses for each operation type. This segmentation enables the system to maintain a single shared address path while preventing address conflicts through dedicated counter management for each operation category.
2Productivity
If multiple refresh operations are performed on a memory bank, then productivity is improved by refreshing multiple rows, but reliability worsens due to increased probability of address path conflicts with access operations
Solution Approach 1:
The patent implements preliminary action by pre-incrementing the refresh counter before executing refresh operations. When a refresh command is received, the refresh counter is incremented in advance to point to the next row address, ensuring that even if multiple refresh operations are queued, each operation retrieves the correct pre-calculated address from the counter without conflicting with simultaneous access operations.
3Device complexity
If the same counter is used for both refresh and access operations, then device complexity is reduced, but reliability deteriorates due to inability to distinguish between refresh row addresses and access row addresses
Solution Approach 1:
The patent segments the counter resource by providing separate counters: a refresh counter dedicated to tracking row addresses for refresh operations and an access counter for access operations. This segmentation allows the system to maintain simple overall structure while ensuring reliable operation differentiation through dedicated counter instances that cannot interfere with each other's addressing.
Data Source
AI summary
A system includes multiple memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address input circuit coupled to the address path that refreshes a first set of memory banks via the address path and, when the command address input circuit refreshes the first set of memory banks, activates a row of a second set of memory banks to store the data or read the data from the row of the second set of memory banks via the address path.