Semiconductor Memory Bank Refresh Control Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices consume high peak current during refresh operations, especially when not all banks are refreshed, leading to increased power consumption in low power systems.
Innovation Solution
A semiconductor memory device with an extended mode register set and a bank refresh block that performs refresh operations in sequence to each bank, using a self refresh pulse generator and decoders to generate sequential enable signals based on array self refresh codes, reducing peak current by enabling banks sequentially regardless of the number of banks being refreshed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all banks are enabled simultaneously in self refresh operation, then refresh operation can be performed to all banks, but high peak current is consumed repeatedly
Solution Approach 1:
The refresh operation is segmented into sequential operations across multiple banks. Instead of enabling all banks simultaneously, the system enables banks one after another in a predetermined sequence, dividing the simultaneous refresh operation into discrete temporal segments that reduce peak current demands while maintaining data retention across all banks
2Power
If all banks are enabled orderly in sequence, then power consumption is reduced, but refresh operation time increases
Solution Approach 1:
The system implements periodic self refresh operations where banks are enabled in sequential order through predetermined address signals. This periodic sequential enabling maintains power efficiency while ensuring all banks receive refresh operations within acceptable time frames by cycling through the bank sequence repeatedly
3Productivity
If piled refresh is executed to selected banks, then refresh operation is performed efficiently, but peak current increases when not all banks are refreshed
Solution Approach 1:
The system inverts the conventional approach by always enabling banks in sequential order regardless of which specific banks need refreshing. Instead of selectively enabling only the required banks (which causes peak current), the sequential enabling of banks in a predetermined sequence is maintained, and the refresh operation is performed on the specific banks that need it within this sequential framework, thus reducing peak current while maintaining efficiency
Data Source
AI summary
A semiconductor memory device having a plurality of banks performs a refresh operation in sequence to each bank whether the refresh operation is required for all or less than all of the banks. The semiconductor memory device includes an extended mode register set containing a refresh information of each bank; and a bank refresh block for supporting a refresh operation performed in sequence to each bank in response to the refresh information of each bank.