Memory Bank Repair Control for Leakage and Soft Error Reduction
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Solution Overview
Problem
As memory devices transition from standby to normal mode, leakage current occurs due to the resupply of power to peripheral circuits, and the decreasing capacitance of memory cells leads to increased soft errors from cosmic rays, such as alpha particles, affecting data integrity.
Innovation Solution
A memory device with a control logic that generates a master disable signal to unused circuits during normal operation, reducing leakage current and implementing repair circuits that operate based on this signal to minimize power consumption and soft errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is resupplied to peripheral circuits when transitioning from standby to normal mode, then the memory device can operate in normal mode, but leakage current occurs
Solution Approach 1:
The patent segments the control signals into multiple types (first control signal for enabling circuit operation, second control signal for disabling leakage current) and applies them at different stages. The master disable signal is segmented to specifically target unused circuits, allowing selective power management that reduces leakage current while maintaining necessary circuit functionality during mode transitions.
Solution Approach 2:
The patent applies preliminary action by generating the master disable signal in advance during the mode transition period. The control logic circuit generates this signal before the leakage current fully develops, and maintains it throughout the transition from standby to normal mode, preventing the harmful effect rather than correcting it after occurrence.
2Quantity of substance
If integration density of memory devices increases, then storage capacity improves, but capacitance of memory cells decreases leading to increased soft errors
Solution Approach 1:
The patent applies preliminary anti-action by using the master disable signal to preemptively counteract the effects of soft errors. When cosmic rays or alpha particles threaten to flip memory cell data during normal operation, the control logic can generate the master disable signal to temporarily disable affected circuits, preventing the soft error from corrupting stored data before it occurs.
Data Source
AI summary
A memory device and an operating method thereof are provided. The memory device includes a memory cell array including a first memory bank and a second memory bank, a control logic configured to control operations of the memory cell array and generate a master enable signal and a master disable signal, a first repair circuit configured to perform a repair operation on memory cells of the first memory bank, and a second repair circuit configured to perform a repair operation on memory cells of the second memory bank. When the memory device is operating in a normal mode, the first repair circuit performs the repair operation, based on the master enable signal, and the second repair circuit does not perform the repair operation, based on the master disable signal.