Memory Bank Repair Using Shared Redundant Bank Shifting

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Solution Overview

Problem

Existing memory devices face inefficiencies due to the large number of redundant banks required for failed main banks, leading to wasted chip area and reduced flexibility in repair schemes, as well as increased data line skew and routing length.

Innovation Solution

A memory device design with a smaller number of redundant banks than main banks, utilizing a data shift-based repair scheme where redundant banks can replace any failed main bank without dedicated coupling, reducing waste and skew by allowing data to be shifted between adjacent banks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large number of redundant banks are provided for each failed main bank, then repair reliability is improved, but chip area is increased and device complexity is increased

Engineering Contradiction:
Improverepair reliabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent implements a repair scheme where a single redundant bank can serve multiple main banks through dynamic data shifting. The I/O circuit is configured to direct data to or from either bank in each pair of adjacent banks, allowing one redundant bank to replace any failed main bank in its pair, thereby reducing the total number of redundant banks needed while maintaining repair reliability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the functionality of multiple dedicated redundant banks into a single shared redundant bank within each pair. By combining the repair capability for multiple main banks into one redundant bank through the I/O circuit's flexible data directing capability, the chip area required for redundant banks is significantly reduced

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If dedicated coupling between redundant banks and main banks is implemented, then repair reliability is improved, but routing length is increased and data line skew is increased

Engineering Contradiction:
Improverepair reliabilityVSAvoidrouting length
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The I/O circuit is designed with universal data directing capability that can route data to or from either bank in each pair of adjacent banks. This multi-functional routing approach eliminates the need for dedicated long coupling paths between specific redundant banks and main banks, reducing routing length and data line skew while maintaining the ability to perform repairs

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If dedicated coupling between redundant banks and main banks is implemented, then repair reliability is improved, but device complexity is increased

Engineering Contradiction:
Improverepair reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs a universal I/O circuit design that can direct data to or from either bank in each pair of adjacent banks through control logic. This approach reduces device complexity by eliminating dedicated coupling paths and instead using a flexible, programmable data directing mechanism that handles repair operations for any failed main bank through software-controlled bank selection

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The repair scheme introduces dynamic bank selection capability where the I/O circuit can flexibly direct data to different banks based on which main bank has failed. This dynamic approach replaces static dedicated couplings, reducing structural complexity while maintaining repair functionality through runtime bank selection based on fail information

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11862270B2Memory device with failed main bank repair using redundant bank
Publication Date: 2024.01.02 YANGTZE MEMORY TECH CO LTD
  • US11862270B2 patent drawing
  • US11862270B2 patent drawing
  • US11862270B2 patent drawing

AI summary

In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and control logic coupled to the I/O circuit. The array of memory cells includes a plurality of banks including a plurality of main banks and a redundant bank. The I/O circuit is coupled to each pair of adjacent banks of the plurality of banks and configured to direct a piece of data to or from either bank of each pair of adjacent banks. The control circuit is configured to select one bank of each pair of adjacent banks based on bank fail information indicative of a failed main bank of the plurality of main banks. The control circuit is further configured to control the I/O circuit to direct the piece of data to or from the selected bank of each pair of adjacent banks.