Memory Bank Repair Using Data Shift and Redundant Bank Swapping

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Solution Overview

Problem

Existing memory devices face issues with redundant bank designs that waste chip area and reduce flexibility due to a large number of unused redundant banks and increased data line skew from lengthy routing, especially in NAND Flash memory devices.

Innovation Solution

Implement a memory device with a smaller number of redundant banks and a flexible, data shift-based repair scheme using multiplexers to couple adjacent banks, allowing data to be shifted between main and redundant banks, reducing redundant bank area and data line skew.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large number of redundant banks are provided in the memory device, then repair capability is improved, but chip area is wasted and device complexity increases

Engineering Contradiction:
Improverepair capabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent implements a universal repair mechanism where a single redundant bank can replace any failed main bank through bank swapping. The redundant bank is designed to be compatible with all main banks, allowing it to assume the identity and function of any failed bank. This multi-functional approach eliminates the need for dedicated redundant banks for each main bank, significantly reducing the total number of redundant banks required while maintaining full repair capability across the memory device.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs a bank swapping mechanism where the identity and configuration of a failed main bank are transferred to a redundant bank. The redundant bank effectively 'recovers' the functional characteristics of the failed bank through this identity transfer process. This allows the memory system to discard the failed bank and recover its functionality in the redundant bank, eliminating the need for extensive redundant banking structures.

Inventive Principle:
Principle #34Discarding and recovering

2Reliability

If many redundant banks are coupled to main banks with lengthy routing, then repair capability is improved, but data line skew increases and manufacturing precision requirements worsen

Engineering Contradiction:
Improverepair capabilityVSAvoiddata line skew
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent extracts the redundant banks from their traditional positions and consolidates them into a single shared redundant bank location. This extraction eliminates the need for lengthy routing connections from multiple main banks to multiple redundant banks. The single shared redundant bank requires minimal routing, significantly reducing data line skew and relaxing manufacturing precision requirements while maintaining the ability to repair any failed main bank.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If a traditional redundant bank design is used, then repair functionality is provided, but flexibility is reduced due to fixed bank identities

Engineering Contradiction:
Improverepair functionalityVSAvoidrepair flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic bank identity assignment where the redundant bank can assume the identity of any failed main bank based on which bank actually fails. This dynamic reconfiguration capability provides maximum flexibility, as the system can adapt to any failure pattern. The bank swapping mechanism allows the redundant bank to dynamically take on the role of the failed bank, enabling flexible repair strategies that were not possible with static, pre-assigned redundant banks.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12554415B2Memory device with failed main bank repair using redundant bank
Publication Date: 2026.02.17 YANGTZE MEMORY TECH CO LTD
  • US12554415B2 patent drawing
  • US12554415B2 patent drawing
  • US12554415B2 patent drawing

AI summary

In certain aspects, a memory device includes an array of memory cells and an input/output (I/O) circuit. The array of memory cells includes N main banks and M redundant banks. Each of N and M is a positive integer, and N is greater than M. The I/O circuit includes a set of write multiplexers (MUXs) respectively coupled to the N main banks and M redundant banks. Each of the N main banks and M redundant banks is coupled to an individual write MUX of the set of write MUXs.