Memory Bank Resident Processor for Lower Command Transfer Latency
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Solution Overview
Problem
Existing memory devices face inefficiencies due to external control circuitry, leading to bandwidth bottlenecks and reduced performance, especially in IoT applications where multiple memory devices ingest and transfer data to a host, resulting in increased command transfer times and power consumption.
Innovation Solution
Incorporating a system processor resident on the memory device to control memory operations locally, reducing the need for external command transfers and enabling processing-in-memory (PIM) operations, thereby decreasing command latency and bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory devices use external control circuitry to manage memory operations, then device complexity is reduced and ease of manufacture is improved, but command transfer times increase and processing performance deteriorates
Solution Approach 1:
The memory device incorporates a system processor resident on the memory device itself, enabling the memory device to autonomously control memory operations without requiring external control circuitry. This self-service approach allows the memory device to execute instructions and manage data locally, reducing command transfer times while maintaining manufacturing simplicity through integrated circuit design
2Device complexity
If memory devices transfer all data processing tasks to external processors, then device complexity is reduced, but bandwidth requirements increase and processing efficiency deteriorates
Solution Approach 1:
The system divides processing tasks between the resident system processor on the memory device and external processors. The system processor handles memory management and data preparation locally, while external processors focus on higher-level computation. This segmentation reduces the need for continuous data transfer over bandwidth-limited interfaces, improving overall processing efficiency while maintaining manageable device complexity
Solution Approach 2:
The patent introduces a new dimension of processing by placing computation capabilities directly within the memory device architecture. This creates a hybrid architecture that combines storage and processing in one location, effectively adding a spatial dimension to the traditional separation of memory and processor, thereby improving productivity without excessively increasing device complexity
3Productivity
If multiple memory devices transfer data to a host simultaneously, then data throughput is improved, but command transfer times increase and power consumption rises
Solution Approach 1:
The system processor resident on each memory device performs data preparation, filtering, and pre-processing operations before data transfer to the host. By completing these operations locally in advance, the memory devices reduce the volume and complexity of data that needs to be transferred over the interface, thereby reducing power consumption during simultaneous transfers while maintaining high data throughput through efficient local processing
Data Source
AI summary
An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.