Memory Bank Segmentation for 10-Bit Data Storage Efficiency
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Solution Overview
Problem
Current processors inefficiently store 10-bit or 12-bit data by allocating 16-bit memory space, leading to increased costs and performance degradation due to wasteful memory usage.
Innovation Solution
A memory apparatus with multiple banks, where a memory controller allocates addresses in 8-bit and 2-bit units, allowing for efficient storage and processing of 10-bit or 12-bit data by dividing data into upper and lower unit parts and combining them across different memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 16-bit memory space is allocated to store 10-bit data in current processors, then data storage capacity is sufficient, but memory usage efficiency deteriorates
Solution Approach 1:
The patent divides the memory system into multiple memory banks (first memory bank and second memory bank) with different address allocation units. The first memory bank uses 8-bit address units while the second memory bank uses 2-bit address units, allowing 10-bit data to be segmented and stored across these banks according to their respective address units, thereby achieving efficient memory utilization without wasting space
Solution Approach 2:
The patent implements dynamic address allocation where the memory controller selectively allocates addresses in 8-bit units for some memory banks and 2-bit units for others based on the data width requirements. This dynamic adaptation allows the memory system to efficiently handle both 8-bit and 10-bit data without fixed overhead, resolving the contradiction between capacity and efficiency
2Quantity of substance
If 16-bit memory space is allocated for 10-bit data storage, then storage capacity is adequate, but system cost increases
Solution Approach 1:
By segmenting the memory into banks with different address units (8-bit and 2-bit), the system avoids allocating full 16-bit space for 10-bit data. Instead, it uses the minimum necessary space in each bank, reducing overall memory capacity requirements and thereby lowering system cost while maintaining adequate storage capability
3Adaptability or versatility
If addresses are allocated in 8-bit units for all memory banks, then compatibility with existing memory structures is maintained, but efficiency in storing 10-bit data deteriorates
Solution Approach 1:
The patent segments the memory system into two types of memory banks: first memory banks that maintain 8-bit address unit compatibility with existing structures, and second memory banks that use 2-bit address units for improved 10-bit data efficiency. This segmentation allows the system to preserve compatibility where needed while achieving efficiency improvements in specific areas
Solution Approach 2:
The memory controller implements multi-functional address allocation, selectively applying 8-bit address units for compatibility with existing memory structures and 2-bit address units for optimized 10-bit data storage. This universal approach allows the same memory system to serve both compatibility and efficiency requirements
Data Source
AI summary
A memory apparatus and a method for processing data the same are suggested to process 10-bit or 12-bit data. A processor that uses 10-bit or 12-bit data can efficiently store 10-bit or 12-bit data and provide a flexible memory access method that reduces memory usage. To this end, by adding a new memory bank that is ¼ of the size of an existing memory bank word, when storing data in 10-bit units, 2 out of 10 bits can be stored in a new memory bank to reduce memory waste. In addition, when 8-bit data is stored using a flexible memory structure, data can be stored in the same way as a previously operated memory bank.