Semiconductor Memory Bank Segmentation for 16-bit Pre-fetch
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Solution Overview
Problem
The transition from an 8-bit pre-fetch scheme to a 16-bit pre-fetch scheme in semiconductor memory devices increases the number of data lines, leading to concerns about reduced chip area and increased current consumption due to higher parallel processing requirements.
Innovation Solution
A semiconductor memory device design that divides its memory bank into odd-numbered and even-numbered array regions, using separate local lines for each, with a column address generation unit controlling the sequence based on the column address's parity, and shared global lines to minimize the increase in data transmission lines and support a 16-bit pre-fetch scheme.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a 16-bit pre-fetch scheme is applied to increase data throughput, then productivity is improved, but the number of data lines increases leading to reduced chip area and increased current consumption
Solution Approach 1:
The memory bank is divided into two separate array regions: an odd-numbered array region and an even-numbered array region. Each region has its own set of local lines (N first local lines for odd region, N second local lines for even region), allowing independent data access paths that share global lines, thereby reducing the total number of lines required compared to a fully parallel 16-bit implementation
Solution Approach 2:
The patent merges the global lines used by both odd and even array regions into a shared set of N global lines. This consolidation allows data from both array regions to be transmitted through common global pathways, significantly reducing the total line count while maintaining 16-bit pre-fetch capability through coordinated access to the shared global line infrastructure
2Productivity
If a 16-bit pre-fetch scheme is applied to increase data throughput, then productivity is improved, but current consumption increases due to higher parallel processing requirements
Solution Approach 1:
By segmenting the memory bank into odd and even array regions with separate local line access paths, the patent enables sequential or interleaved access patterns that reduce simultaneous switching activity compared to fully parallel 16-bit access, thereby lowering dynamic power consumption while maintaining high throughput
Solution Approach 2:
The shared global lines reduce the total number of active signal paths in the system. By having both array regions share N global lines rather than each having dedicated 16-bit wide global line sets, the patent reduces capacitive loading and switching activity, directly reducing current consumption while preserving data throughput through coordinated access protocols
3Reliability
If separate local lines are used for odd and even array regions to support 16-bit pre-fetch, then reliability is improved through adequate sensing and amplifying time, but device complexity increases without additional selection means
Solution Approach 1:
The patent segments the memory bank into odd and even array regions, each with dedicated local lines for data access. This segmentation provides separate, interference-free data paths that ensure adequate sensing and amplifying time for each region without requiring complex selection logic, as each region independently accesses its own local lines before sharing global lines
Solution Approach 2:
The patent merges the global line infrastructure to be shared by both odd and even array regions. This consolidation reduces device complexity by eliminating the need for separate global line sets and associated selection means, while the segmented local line access ensures that each region maintains reliable sensing and amplifying time through dedicated access paths that prevent signal interference
Data Source
AI summary
Disclosed herein is a semiconductor memory device using a pre-fetch method and a semiconductor system including the same. The semiconductor memory device may include a memory bank having an odd-numbered array region suitable for inputting/outputting data through N first local lines in response to an odd-numbered column address, and an even-numbered array region suitable for inputting/outputting data through N second local lines in response to an even-numbered column address, N being a positive integer, a column address generation unit suitable for consecutively generating the odd-numbered column address and the even-numbered column address whose generation sequence is controlled depending on whether an external column address has an even-numbered value or an odd-numbered value, and N global lines coupled in common to the N first local lines and the N second local lines, suitable for inputting/outputting data.