Memory Bank Segmentation for Error Correction Efficiency
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Solution Overview
Problem
As memory device capacity increases, it becomes challenging to fabricate devices without defective memory cells, leading to the need for error correction methods such as redundant cells and error correction circuits to address errors in memory cells.
Innovation Solution
The proposed memory system includes a configuration with multiple row and column lines, bit line sense amplifiers, and a selector to efficiently activate and read/write data from memory cells, optimizing error correction by avoiding adjacent column line data access during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device capacity is increased, then storage capability is improved, but the likelihood of defective memory cells increases
Solution Approach 1:
The memory device is divided into multiple banks, with each bank containing independent memory cells and error correction circuits. This segmentation allows errors to be isolated to specific banks, preventing a single defective cell from affecting the entire memory device and enabling targeted error correction.
Solution Approach 2:
An error correction circuit is introduced as an intermediary component between the memory cells and the data processing system. This circuit detects and corrects errors in read data before it reaches the processor, and prepares data for write operations, thereby mediating the impact of defective memory cells.
2Reliability
If error correction circuits are used, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The error correction functionality is segmented into distributed error correction circuits within each bank, rather than a single complex centralized circuit. Each bank's error correction circuit handles only the errors in its own memory cells, reducing the complexity of individual circuits while maintaining overall error correction capability.
Solution Approach 2:
Each bank is equipped with its own error correction circuit that autonomously detects and corrects errors in its memory cells without requiring intervention from other banks or external systems. This self-service approach simplifies the overall system architecture by distributing the error correction burden.
3Reliability
If redundant memory cells are used, then error correction capability is improved, but manufacturing complexity increases
Solution Approach 1:
Redundant memory cells are organized into separate repairable regions within each bank, allowing defective cells to be identified and replaced with redundant cells through bank-specific repair processes. This segmentation simplifies the repair process compared to treating the entire memory device as a single unit.
Solution Approach 2:
Redundant memory cells are pre-configured within each bank during manufacturing, ready to replace defective cells that may be discovered during testing or operation. This preliminary preparation of redundant cells within manageable bank units simplifies the overall repair process.
Data Source
AI summary
A memory includes: a plurality of row lines; a plurality of column lines; and a plurality of memory cells each of which is coupled to one row line among the row lines and one column line among the column lines, wherein memory cells corresponding to a row line which is selected based on a row address among the row lines are simultaneously activated, and data are read from memory cells corresponding to column lines which are selected based on a column address among the activated memory cells, and the selected column lines are not adjacent to each other.