Semiconductor Memory Bank Segmentation for Layout Efficiency
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Solution Overview
Problem
Conventional semiconductor memory apparatuses face challenges in securing a layout margin due to the increasing number of data input/output lines required for higher processing capacities, which can lead to difficulties in data transmission and storage operations.
Innovation Solution
The semiconductor memory apparatus is designed with memory banks divided into up banks and down banks, with separate data input/output lines for each, allowing for selective communication based on input/output modes, reducing the overall number of data input/output lines needed and improving layout efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of data input/output lines is increased to handle higher processing capacity, then the data transmission capability is improved, but the layout margin is reduced
Solution Approach 1:
The memory banks are divided into up banks and down banks, with separate data input/output lines for each. This segmentation allows independent data transmission paths, improving data transmission capability while maintaining compact layout by utilizing vertical space efficiently.
2Productivity
If separate data input/output lines are provided for up banks and down banks, then data transmission efficiency is improved, but the number of lines increases
Solution Approach 1:
The data input/output lines for up banks and down banks are merged into a common set of lines that can be selectively activated. Through selective communication based on input/output modes, the system achieves efficient data transmission without requiring fully separate line sets for each bank type.
Solution Approach 2:
The system dynamically selects which data input/output lines to use based on the operational mode (reading from or writing to up banks or down banks). This dynamic allocation allows the same physical lines to serve multiple functions, reducing the total number of lines needed while maintaining high data transmission efficiency.
Data Source
AI summary
A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.