Memory System Bank Segmentation for Word Line Load Management
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Solution Overview
Problem
Three-dimensional cell arrays in memory systems, such as those using carbon nanotube (CNT) based cross-point type memory cells, face challenges in increasing capacity while managing the load on selection lines and preventing overload due to parallel access, which leads to inefficiencies in data storage and retrieval.
Innovation Solution
The memory system employs a write sequence that divides the access of memory cells into high and low resistance states, using impedance switching write buffers to control the impedance between selection lines and voltage generators, allowing for simultaneous access while minimizing the load on word lines by distributing the current load through time-division and majority decision logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional cell arrays are used to increase memory capacity, then the storage capacity is improved, but the load on selection lines increases causing overload
Solution Approach 1:
The cell array is divided into multiple banks, with each bank having its own independent selection lines. This segmentation allows parallel access to multiple banks simultaneously without overloading a single selection line, as each bank operates independently with dedicated control lines.
Solution Approach 2:
The patent transitions from a two-dimensional cell array to a three-dimensional structure by stacking multiple banks in the vertical dimension. This enables increased storage capacity while maintaining manageable selection line loads through the bank-based organizational structure.
2Speed
If parallel simultaneous accesses are made to multiple memory cells, then the data retrieval speed is improved, but the load on shared selection lines increases
Solution Approach 1:
By segmenting the memory into multiple banks with independent selection lines, the patent enables true parallel access across banks without the selection line contention that would occur in a unified array. Each bank can be accessed simultaneously through its own dedicated selection lines.
Solution Approach 2:
The bank structure acts as an intermediary layer between the selection lines and memory cells, distributing access requests across multiple independent pathways. This mediation prevents direct contention on shared lines while enabling parallel operations.
3Quantity of substance
If more memory cells are connected to one selection line to increase capacity, then the storage density is improved, but the cell share decreases due to massive driving circuits
Solution Approach 1:
The memory is divided into multiple smaller banks, each with its own selection lines and driving circuits. This segmentation reduces the complexity of driving circuits per bank while maintaining high overall storage density through the combined capacity of all banks.
Solution Approach 2:
By organizing memory banks in three dimensions (stacking multiple banks vertically), the patent achieves high storage density without requiring excessively complex driving circuits, as each bank maintains a manageable size with proportional circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the load on word lines during data writing and reading, maintaining symmetry in cell area while increasing the number of accessible memory cells per word line, thereby enhancing the scalability and efficiency of the memory system without increasing the complexity of the cell structure.
Implementation Method 1
When phonon energy accumulated in the NT stack reaches a certain level or higher, the resistance state of the NT stack changes to a high resistance state
Implementation Method 2
Joule heat required for making phonons is represented by i2r in FIG. 4
Data Source
AI summary
A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different resistance states; and an access circuit operative to execute a write sequence of changing the resistance state for writing data in the memory cell, wherein the access circuit, on the write sequence, executes a first step of changing all memory cells provided at the intersections of access first lines and the access and fault second lines to the high resistance state, and a second step of changing all or part of access cells connected to the access second line to the low resistance state.