Memory Bank Segmentation to Reduce DRAM Signal-Line Parasitics
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Solution Overview
Problem
The high power consumption and inefficiencies in Dynamic Random Access Memory (DRAM) due to parasitic resistance and capacitance in data signal lines, as well as the limitations of Error Correction Coding (ECC) in correcting multiple-bit errors, particularly adjacent bit errors, are unresolved issues.
Innovation Solution
The memory bank design includes memory arrays divided into array units connected by separate data signal lines to reduce parasitic resistance and capacitance, and incorporates multiple ECC units to handle simultaneous errors by dividing data into parts for separate correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data signal lines connect read-write control circuits to multiple array units, then data transmission capability is improved, but parasitic resistance and capacitance increase causing high power consumption
Solution Approach 1:
The patent divides each memory array into multiple array units (first array unit and second array unit), with each array unit having separate data signal line connections to read-write control circuits. This segmentation reduces the number of array units connected to a single read-write control circuit, thereby reducing parasitic resistance and capacitance on data signal lines and lowering power consumption while maintaining data transmission capability.
2Device complexity
If read-write control circuits are centralized to simplify control, then device complexity is reduced, but signal line length increases causing higher parasitic resistance and power consumption
Solution Approach 1:
The patent places read-write control circuits between adjacent memory arrays, creating a distributed control architecture. This local arrangement reduces the distance between read-write control circuits and array units, shortening data signal line lengths and reducing parasitic resistance and capacitance, thereby lowering power consumption while maintaining control functionality.
3Reliability
If traditional ECC is used to correct errors, then single-bit errors are corrected, but multiple-bit errors particularly adjacent bit errors cannot be corrected
Solution Approach 1:
The patent divides memory arrays into separate array units with independent data signal line connections to read-write control circuits. This segmentation isolates adjacent bit groups, reducing the probability that multiple-bit errors (particularly adjacent bit errors) occur simultaneously in the same data transmission path. Combined with ECC, this provides enhanced error correction capability for both single-bit and multiple-bit errors.
Data Source
AI summary
The present disclosure provides a memory bank and a memory. The memory bank includes: multiple memory arrays arranged along a first direction, each of the memory arrays being divided into at least two array units along a second direction, and the first direction and the second direction being perpendicular to each other; multiple read-write control circuits, the read-write control circuits being provided between adjacent two of the memory arrays; and multiple data signal lines configured to electrically connect the read-write control circuits and the array units; wherein, different array units of each of the memory arrays are electrically connected to different read-write control circuits through different data signal lines.