Memory Bank Segmentation for Rotated Image Bandwidth
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Solution Overview
Problem
Conventional SDRAM memory technologies face inefficiencies when handling rotated images or video due to precharge cycles and pipeline delays, leading to reduced memory bandwidth and resolution loss during rotation processes.
Innovation Solution
The proposed solution involves an algorithm that writes pixels from different video lines to different memory banks, eliminating precharge delays and pipeline delays, and incorporates an expansion routine in the first pass of a two-pass rotation method to maintain image resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If pixels from different video lines are written to the same memory row, then memory structure is simple, but precharge delays occur between row accesses reducing memory bandwidth
Solution Approach 1:
The patent divides the memory access operation into segments by utilizing multiple memory banks. Instead of accessing all pixels sequentially from a single row, the system segments the video data across multiple banks, allowing parallel access to different bank groups. This segmentation eliminates the precharge delay bottleneck by enabling concurrent memory operations across separate bank groups, thereby maintaining high memory bandwidth without increasing overall memory structure complexity.
2Ease of operation
If conventional two-pass rotation method is used, then image rotation is achieved, but resolution is lost due to image shrinking in the first pass
Solution Approach 1:
The patent applies preliminary expansion action during the first pass of the rotation process. Before the actual rotation occurs, the image is expanded to compensate for the shrinking that would normally happen. This preliminary expansion ensures that when the rotation is completed in the second pass, the final image maintains its original resolution without the quality loss typically associated with conventional two-pass rotation methods.
3Device complexity
If pipeline delay is not addressed in multi-port applications, then memory controller design is simple, but significant delay occurs between access to different images reducing effective memory bandwidth
Solution Approach 1:
The patent implements periodic action by establishing a systematic pipeline delay compensation mechanism that operates in regular intervals. The memory controller is designed to anticipate and compensate for pipeline delays through periodic flushing and scheduling of memory operations. This approach maintains simple memory controller design while significantly reducing access delays between different images by rhythmically managing the pipeline flow and ensuring that no single operation bottlenecks the overall system performance.
Data Source
AI summary
A system and method of improving access to digital image files by combining close and activation cycles within a memory device into a single step and eliminating a pipeline delay in the process. The system and method further enhance data access efficiencies by sequential storage of successive video lines or elements of video lines in different banks with the same memory device. The techniques used to improve access to digital image data may be particularly useful when accessing digital image files that may have been rotated.