Memory Controller Bank Segmentation for Address Table Optimization
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Solution Overview
Problem
Current memory systems with nonvolatile memory face challenges in supporting fine access granularity while minimizing the increase in address translation table size, leading to high write amplification and increased size of the address translation table.
Innovation Solution
The memory system divides the logical address space into 2N banks and corresponding physical storage regions, using a controller that manages an address translation table in random access memory and allocates write buffers for each bank, allowing for efficient write operations and reduced page table size by storing only region-specific location information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the address translation unit is reduced to support fine access granularity, then the access granularity is improved, but the size of the address translation table increases
Solution Approach 1:
The logical address space is divided into multiple banks (2N banks), and the address translation table is segmented into multiple page tables corresponding to each bank. This segmentation allows the system to support fine access granularity while keeping each individual page table size manageable, as each page table only needs to translate addresses within its specific bank rather than the entire address space.
Solution Approach 2:
The patent introduces a bank dimension to the address translation structure. Instead of a single flat page table, the system uses multiple page tables organized in a hierarchical structure with banks as an additional dimension. This dimensional organization allows efficient translation of fine-grained addresses while distributing the table size across multiple smaller units.
2Adaptability or versatility
If read modify write operation is executed to rewrite partial data, then the data update capability is improved, but the write amplification increases
Solution Approach 1:
The patent segments the logical address space into banks and associates each bank with dedicated write buffers. This segmentation allows the system to handle partial data updates more efficiently by directing writes to specific banks and their corresponding buffers, reducing the need for full-page read-modify-write operations and thereby reducing write amplification.
Solution Approach 2:
Write buffers are introduced as intermediary structures between the host and the nonvolatile memory. These buffers temporarily hold write data, allowing the system to batch and optimize write operations. By using write buffers, the system can reduce the frequency of writes to the nonvolatile memory, thereby reducing write amplification while maintaining data update capability.
Data Source
AI summary
According to one embodiment, a controller of a memory system manages 2N banks obtained by dividing a logical address space, and 2N regions included in a nonvolatile memory, the 2N regions corresponding one-to-one to the 2N banks. The controller stores an address translation table in a random access memory, the address translation table including a plurality of entries respectively corresponding to a plurality of logical addresses which are contiguous in units of a first size corresponding to granularity of data read/write-accessed by a host, the address translation table managing mapping between each of the logical addresses and each of physical addresses. The controller allocates 2N write buffers to the random access memory.