Memory Bank Access via Segmented Data Channels
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Solution Overview
Problem
Memory devices face limitations in accessing data across multiple banks due to the need for concurrent access operations, which restricts the number of addressable banks and increases access time.
Innovation Solution
The memory system enables the use of a single bank for both first and second access operations, allowing all banks to be accessible by communicating the second access data on the same data channels as the first access operation, and by receiving data transfer type messages from the host system to determine the necessity of additional access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If concurrent access operations are used across multiple banks, then access speed is improved, but the number of addressable banks is restricted
Solution Approach 1:
The memory system segments data channels into first and second subsets, allowing different banks to be accessed through different channel subsets. This segmentation enables the memory device to address more banks than previously possible by distributing access operations across multiple channel groups, thereby resolving the contradiction between access speed and the number of addressable banks.
Solution Approach 2:
The patent introduces a new dimension of data channel organization by dividing channels into multiple subsets and associating them with different banks. This dimensional reorganization allows concurrent access to multiple banks through different channel subsets, expanding the number of addressable banks while maintaining high access speed through parallel operations.
2Speed
If concurrent access operations are used across multiple banks, then access speed is improved, but access time between operations increases
Solution Approach 1:
The memory device performs preliminary actions by pre-fetching and buffering data in intermediate storage structures before it is needed. This allows the system to prepare data for subsequent access operations in advance, reducing the access time between operations while maintaining high access speed through efficient data staging and prefetching mechanisms.
Solution Approach 2:
The patent implements continuous useful action by maintaining data in intermediate buffers and storage structures between access operations. This continuity allows the memory system to keep data readily available for subsequent accesses without requiring full bank access cycles, thereby reducing the time loss between operations while sustaining high access speeds.
3Adaptability or versatility
If data is communicated on separate data channels, then access flexibility is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing data channels and control logic that can serve multiple banks and access patterns through a unified architecture. The same data channel infrastructure is used for both first and second subset operations, allowing the system to achieve access flexibility without proportionally increasing device complexity, as the channels perform multiple functions across different bank access scenarios.
Data Source
AI summary
Methods, systems, and devices for capability messaging for memory operations across banks with multiple page access are described. Techniques are described for a memory system to use a same bank for first and second access operations of data associated with an access command. The data corresponding to the second access operation may be communicated after the data corresponding to the first access operation on the same data channels. Techniques are further described for including one or more additional access commands with the access command that use other banks. Techniques are further described for interleaving data sets communicated as a result of the access commands and for abutting data sets based on parameters obtained by the memory device. Techniques are further described for the generation and performance of internal access commands in accordance with a data transfer type indicated by a host system.