Memory Bank ECC Layout for Selective Parity Error Correction
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in maintaining yield and reliability due to the overhead of error correction circuits and increased Soft Error Rate (SER) from electromagnetic interference, particularly as chip size and integration increase.
Innovation Solution
A semiconductor memory device with a separate memory bank for error detection and correction, where parity data is generated and stored only for important data or in regions with weak reliability, using a mode setting circuit to control flag signals for selective error correction, reducing the overhead of error detection and correction circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction circuits are applied to all memory banks, then reliability is improved, but device complexity and overhead increase
Solution Approach 1:
The patent applies error correction capability selectively to specific memory banks rather than uniformly across all banks. The memory device includes a mix of ECC-enabled banks and non-ECC banks, allowing reliability enhancement only where needed based on application requirements, thus reducing overall device complexity and overhead.
Solution Approach 2:
The patent introduces a mode setting circuit that can dynamically configure which memory banks operate with ECC capability. Through control signals and flag settings, the system can adaptively enable or disable ECC for different banks based on runtime requirements, optimizing the balance between reliability and complexity.
2Productivity
If chip size increases to achieve high integration, then performance is improved, but yield decreases
Solution Approach 1:
The patent implements ECC capability in a localized manner within the memory chip, allowing high integration performance while maintaining yield through selective error correction. By enabling ECC only in specific banks rather than across the entire large chip, the system maintains reliability without the overhead penalty of universal ECC implementation.
3Reliability
If parity cells are added for ECC, then reliability is improved, but chip size increases
Solution Approach 1:
The patent reduces chip size impact by concentrating parity cells only in the memory banks that require ECC capability. Instead of distributing parity cells across all banks, the system localizes them to specific banks, thereby achieving error detection and correction with minimal area overhead.
4Reliability
If error correction is applied to all data, then reliability is improved, but speed delay increases
Solution Approach 1:
The patent applies error correction only partially to specific memory banks rather than to all data operations. This selective approach reduces the speed delay overhead by limiting ECC processing to only those banks where reliability is critical, while allowing faster access in non-ECC banks for less critical data.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.