Dynamic Memory Bank Separation for Double-Bit Error Mitigation
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Solution Overview
Problem
Computer memory devices are susceptible to soft errors caused by particle strikes, which can result in single-bit or multiple-bit errors, and existing error correcting codes (ECC) are inadequate in correcting double-bit errors.
Innovation Solution
A memory system that is configurable to operate in either banked mode or bit-separated mode, utilizing multiplexing circuitry to select and combine data from multiple memory banks, optimizing memory bandwidth and power consumption while enhancing reliability against soft errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in traditional banked memory mode, then memory bandwidth and power consumption are optimized, but the memory is susceptible to double-bit errors from particle strikes
Solution Approach 1:
The patent divides the storage of each data item across multiple memory banks by separating individual bits into different banks. Specifically, bits of a single data item are stored in different banks (e.g., even bits in one bank, odd bits in another), so that a particle strike affecting one bank can only cause single-bit errors rather than double-bit errors on the same data item. This segmentation maintains memory bandwidth by allowing parallel access to multiple banks while achieving enhanced error protection.
2Reliability
If error correcting codes (ECC) are used to correct single-bit errors, then soft errors are addressed, but multiple-bit errors cannot be corrected
Solution Approach 1:
The patent implements preliminary error prevention by structuring data storage across multiple banks before particle strikes can occur. By pre-distributing bits of each data item across different banks, the system proactively prevents double-bit errors from occurring in the first place, rather than relying on complex post-error detection and correction mechanisms. This approach simplifies the overall error handling complexity while maintaining high reliability.
Data Source
AI summary
Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.