Semiconductor Memory Bank Strobe Signal Timing Control
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Solution Overview
Problem
Current semiconductor memory apparatuses face challenges in efficiently managing data operations across multiple memory banks, particularly in optimizing data transfer and storage processes, which affects performance and power consumption.
Innovation Solution
The semiconductor memory apparatus incorporates peri-lines, peri-repeaters, bank repeaters, and a control circuit to generate and manage peri-strobe and bank strobe signals based on byte information and memory bank selection, enabling precise timing and operation mode adjustments for data input/output operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer operations are performed across multiple memory banks using traditional control methods, then data storage capacity is increased, but data transfer efficiency deteriorates due to lack of optimized timing control
Solution Approach 1:
The control circuit is segmented into multiple independent components: a peri-repeater control circuit that generates peri-strobe signals, and multiple bank repeater control circuits (first and second bank repeater control circuits) that generate bank strobe signals. Each control circuit independently manages timing for specific data transfer paths, allowing optimized control without requiring a monolithic complex controller.
Solution Approach 2:
The control circuits generate strobe signals in advance based on predetermined timing relationships. The peri-strobe signal timing is determined before data transfer begins, and bank strobe signals are generated based on the peri-strobe signals and byte information. This preliminary timing setup enables efficient data transfer without real-time complex decision-making.
2Use of energy by stationary object
If multiple memory banks operate simultaneously without optimized timing control, then data storage capacity is increased, but power consumption increases due to unnecessary simultaneous operations
Solution Approach 1:
The system dynamically adjusts which memory banks operate based on byte information and memory bank selection information. The control circuits generate strobe signals selectively for active banks only, allowing the system to adapt its operation to actual data transfer needs. This dynamic control prevents unnecessary simultaneous operations across all banks, reducing power consumption while maintaining data operation speed for active banks.
3Productivity
If traditional data transfer methods are used between byte pads and memory banks, then system simplicity is maintained, but data transfer efficiency deteriorates due to lack of staged signal regeneration
Solution Approach 1:
Peri-repeaters and bank repeaters serve as intermediary components between byte pads and memory banks. The peri-repeater receives data from byte pads and generates peri-strobe signals, then passes data to bank repeaters which generate bank strobe signals for final memory bank access. This staged intermediary approach enables efficient signal regeneration and timing control without requiring direct complex control between all components.
4Measurement precision
If precise timing control is implemented for data operations, then data transfer efficiency is improved, but device complexity increases due to multiple strobe signal generation requirements
Solution Approach 1:
The timing control function is segmented across multiple specialized control circuits. The peri-repeater control circuit handles peri-strobe signal timing with high precision, while separate bank repeater control circuits handle bank-specific strobe timing. This segmentation allows each circuit to be optimized for its specific timing requirements without requiring one overly complex universal timer.
Solution Approach 2:
Timing relationships are established in advance through the hierarchical signal generation structure. The peri-strobe signal timing is predetermined, and bank strobe signal timing is predetermined based on the peri-strobe signals and byte information. This preliminary timing setup enables precise control without requiring complex real-time timing calculations during data transfer.
Data Source
AI summary
A semiconductor memory apparatus includes first and second byte pads. A left-side peri-line couples the first byte pad and a first memory bank region and a right-side peri-line couples the second byte pad and a second memory bank region. A peri-repeater couples the left-side peri-line and the right-side peri-line based on a peri-strobe signal. The peri-strobe signal is generated based on byte information and memory bank selection information.