Semiconductor Memory Bank Timing Allocation
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Solution Overview
Problem
Semiconductor memory apparatuses face errors due to uniform read/write operating times, which do not account for varying response speeds among banks, leading to inefficiencies and potential data loss.
Innovation Solution
The semiconductor memory apparatus generates active signals with different enable timings and uses a precharge signal generation unit with delay units to allocate specific read/write operating times to each bank, ensuring compliance with JEDEC standards while optimizing operations for banks with different response speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the same read/write operating time (tRC) is allocated to all banks, then the system maintains simple timing control, but banks with slow response speeds experience errors and data loss
Solution Approach 1:
The patent segments the read/write operating time into bank-specific time periods. Each bank is assigned a dedicated time slot (first time period, second time period, etc.) with customized duration based on its response speed characteristics. This segmentation allows slow-response banks to receive extended time without affecting the timing of other banks, thereby improving data retention reliability while maintaining manageable timing control through structured allocation.
Solution Approach 2:
The patent applies local quality by customizing the read/write operating time duration for each individual bank according to its specific response speed characteristics. Banks with slow response speeds are allocated longer time periods, while faster banks receive standard or shorter periods. This localized optimization ensures each bank operates within its optimal timing parameters, improving overall system reliability without requiring complete redesign of the timing control mechanism.
2Reliability
If the read/write operating time is extended for slow-response banks, then data retention improves, but the overall system productivity decreases due to longer operating cycles
Solution Approach 1:
The patent segments the operating time allocation so that extended time periods for slow-response banks do not propagate to all banks. Each bank operates in its own time slot with customized duration, allowing the system to maintain extended timing where needed while keeping other banks on faster cycles. This segmentation prevents the entire system from being bottlenecked by the slowest bank, thereby preserving productivity while improving reliability for specific banks.
Solution Approach 2:
The patent implements dynamic time allocation where the read/write operating time varies by bank based on measured or characterized response speeds. The timing control unit dynamically assigns appropriate time periods to each bank, allowing the system to adapt to different bank performance characteristics. This dynamic approach ensures that only the necessary banks receive extended timing, optimizing the balance between data retention and overall system throughput.
3Productivity
If different read/write operating times are allocated to different banks, then each bank operates optimally, but the timing control mechanism becomes more complex
Solution Approach 1:
The patent structures the timing control mechanism by segmenting time into distinct, bank-specific periods (first time period, second time period, third time period, etc.). Each segment is associated with a specific bank and has a predetermined duration. This segmented structure provides a clear framework for the timing control unit to manage different time allocations without requiring complex inter-dependent calculations, thereby improving bank operation efficiency while keeping the control mechanism systematically manageable.
Solution Approach 2:
The patent changes the time parameter specifically for each bank based on its response speed characteristics, rather than changing the entire system's timing architecture. The timing control unit adjusts only the duration parameter for individual banks while maintaining the same basic timing structure and control logic. This parameter-based approach allows optimal operation for each bank without proportionally increasing the complexity of the overall timing control mechanism.
Data Source
AI summary
A semiconductor memory apparatus includes an active signal generation unit that generates a plurality of active signals having different enable timings in response to a refresh signal, a precharge signal generation unit that delays at least one of the active signals to generate at least one precharge signal for enabling at least two equalizer signals at the same time, and a sense amplifier driver control unit that generates the plurality of equalizer signals for controlling individual sense amplifier drivers in response to the plurality of active signals and the precharge signal.