Memory Bank Voltage Compensation for Resistance-Induced Drops
Solution Overview
Problem
Conventional semiconductor memory cells experience increased source side body effect and drain side voltage drops as memory capacity increases, leading to wide current distribution variations and reduced programming efficiency due to buried diffusion and metal bit line resistance loading.
Innovation Solution
The memory is divided into banks and sub-banks, with adjusted voltages applied to word lines and bit lines based on the position of memory cells within these banks and sub-banks to compensate for resistance-induced voltage drops, ensuring consistent current distribution and improved programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased, then storage capability is improved, but source side body effect increases and drain side voltage drops
Solution Approach 1:
The memory structure is divided into multiple banks, with each bank having independent bit line voltage compensation circuits. This segmentation allows localized voltage compensation without affecting the entire memory array, enabling large capacity while maintaining voltage stability through distributed compensation nodes.
Solution Approach 2:
Different bit lines in different banks are provided with different voltage compensation amounts based on their specific position and resistance characteristics. This local quality approach ensures that each bit line receives precisely the compensation it needs to offset its specific voltage drop, maintaining uniform current distribution across the entire large-capacity memory.
2Quantity of substance
If memory capacity is increased, then storage capability is improved, but current distribution range broadens
Solution Approach 1:
The invention dynamically adjusts bit line voltages as a parameter to compensate for position-dependent voltage drops. By changing the voltage parameter adaptively based on bank position and resistance characteristics, the current distribution uniformity is maintained across the entire large-capacity memory array.
Solution Approach 2:
The voltage compensation mechanism operates based on feedback from the actual voltage drop characteristics of each bit line. Compensation voltages are applied in response to measured or calculated voltage drops, creating a feedback loop that maintains uniform current distribution despite variations in memory cell position within the large capacity array.
3Productivity
If larger program current is used, then programming speed is improved, but programming efficiency decreases due to voltage drops
Solution Approach 1:
The invention applies voltage compensation to bit lines before programming operations to preemptively counteract the voltage drops that would otherwise occur during high-current programming. This preliminary anti-action allows larger program currents to be used for faster programming while the compensation prevents the associated voltage drops from reducing programming efficiency.
Solution Approach 2:
During programming operations, the bit line voltages are dynamically adjusted as a parameter to maintain optimal programming conditions. The voltage compensation adapts to the programming current level, allowing high-speed programming with maintained efficiency by preventing voltage drops that would otherwise occur under high current conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach narrows the current distribution range, simplifies circuit design, and enhances programming and erasing efficiency by compensating for resistance-related voltage drops, thereby reducing the program disturb effect.
Implementation Method 1
In order to compensate the voltage drop resulting from the resistance of the j-th bit line and the j-th BD region, at least one of the voltage applied to the i-th word line and the voltage applied to the j-th bit line is adjusted according to the position of the bank which the memory cell M (i, j) belongs to
Data Source
AI summary
A memory and a driving method therefor is provided. A j-th bank select MOS transistor is coupled to a j-th bit line and controlled by a bank select line. A j-th BD region is coupled to the j-th bank select MOS transistor. Gate(i, j) of memory cell M (i, j) is coupled to the i-th word line, the first source/drain(i, j) of memory cell M (i, j) is coupled to the j-th BD region, and the second source/drain(i, j) of memory cell M (i, j) is coupled to the first source/drain(i, j+1). In order to compensate the voltage drop resulting from the resistance of the j-th bit line and the j-th BD region, at least one of the voltage applied to the i-th word line and the voltage applied to the j-th bit line is adjusted according to the position of the bank which the memory cell M (i, j) belongs to.