Semiconductor Memory Banks with Heterogeneous Cell Counts
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Solution Overview
Problem
As the number of memory banks in semiconductor memory devices increases to provide more storage capacity, so does current consumption, posing a challenge in balancing storage capacity with power efficiency.
Innovation Solution
The semiconductor memory device incorporates a memory cell array with multiple bank arrays, each comprising a first and second sub bank array, where the number of memory cells coupled to bit-lines and word-lines differs between the sub arrays, allowing for optimized access and reduced current consumption by grouping banks based on address spaces and loading conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory banks is increased to provide more storage capacity, then storage capacity is improved, but current consumption increases
Solution Approach 1:
The memory device is divided into multiple bank arrays with different numbers of memory cells coupled to their bit-lines. This segmentation allows the memory to be organized into heterogeneous banks rather than uniform banks, enabling selective activation and optimized resource utilization that reduces overall current consumption while maintaining high storage capacity.
Solution Approach 2:
Different bank arrays are assigned different numbers of memory cells per bit-line based on local requirements. This creates a non-uniform structure where each bank array has optimized characteristics for its specific function, allowing the system to achieve high storage capacity in certain regions while consuming less current in other regions, thereby reducing total power consumption.
2Quantity of substance
If the number of memory banks is increased to provide more storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple bank arrays with different numbers of memory cells coupled to their bit-lines. This segmentation allows the memory to be organized into heterogeneous banks rather than uniform banks, enabling selective activation and optimized resource utilization that reduces overall current consumption while maintaining high storage capacity.
Solution Approach 2:
The control logic circuit is designed to universally manage multiple bank arrays with different configurations. This multi-functional control approach allows a single control unit to handle heterogeneous bank structures, reducing the need for separate control circuits for each bank type and thereby managing device complexity while achieving high storage capacity.
3Speed
If banks are configured with different numbers of memory cells per bit-line, then operating speed is improved through optimized access, but manufacturing complexity increases
Solution Approach 1:
Different bank arrays are assigned different numbers of memory cells per bit-line based on local requirements. This creates a non-uniform structure where each bank array has optimized characteristics for its specific function, allowing the system to achieve high storage capacity in certain regions while consuming less current in other regions, thereby reducing total power consumption.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a plurality of bank arrays and a control logic circuit. The control logic circuit controls access to the memory cell array in response to a command and an address. A first number of memory cells are coupled to a bit-line of a first bank array of the plurality of bank arrays, a second number of memory cells are coupled to a bit-line of a second bank array of the plurality of bank arrays and the first number is different from the second number.