Semiconductor Memory Banks for Fast Wrap-Around Read Operations
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Solution Overview
Problem
NAND flash memory devices experience slower address transition during continuous read operations compared to NOR memory, leading to delays in accessing management data across page transitions.
Innovation Solution
A semiconductor memory device with two simultaneously accessible memory banks, where a word line selection device performs selective read operations by decoding address information to enable flexible and fast data reading, allowing for concurrent access and reduced latency across page transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If continuous read operation of wrap-around is performed in conventional flash memory, then data can be read sequentially from different pages, but address transition becomes slower and delay time for accessing management data increases
Solution Approach 1:
The memory array is divided into multiple memory banks (at least two), each capable of independent access. This segmentation allows parallel read operations across different banks, enabling the system to overcome the address transition delay by switching to a different bank that contains the required management data while one bank is being read from.
Solution Approach 2:
The patent pre-organizes data and management information across multiple memory banks so that when a read operation is in progress on one bank, the management data for the next page is already available in another bank. This preliminary arrangement eliminates waiting time for address transitions during wrap-around operations.
2Ease of operation
If single memory bank is used for read operations, then device structure is simpler, but continuous read operation across page boundaries experiences delay
Solution Approach 1:
The memory system is segmented into multiple independently accessible memory banks. During continuous read operations, when one bank is being accessed, the controller can switch to another bank to fetch management data, thereby maintaining ease of operation for wrap-around reads without experiencing delays.
Solution Approach 2:
By having multiple memory banks available, the system ensures continuity of useful action during read operations. While one bank is being read from, another bank can be accessed for management data, eliminating idle time and maintaining continuous data flow during wrap-around operations.
Data Source
AI summary
A semiconductor memory device, having a memory array which has two memory banks which can be accessed simultaneously is provided. A word line selection circuit selects the word line according to the row address information, and a controller controls the word line selection circuit according to the received instruction. The controller performs the first read operation of the word line selection circuit in response to a first read command, and performs the second read operation of the word line selection circuit in response to a second read command. The first read operation selects the n-th word line of one of the memory banks and selects the (n+1)-th or (n−1)-th word line of the other memory bank, and the second read operation selects the n-th word line of one of the memory banks and selects the n-th word line of the other memory bank.