Resistive Memory Barrier Layer for Lower Step Height
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Solution Overview
Problem
Resistive memory devices, such as ReRAM, face challenges with thick barrier layers that increase step height, leading to higher fabrication costs, longer processing times, and integration issues in advanced technology nodes, along with uneven thickness and damage to dielectric etch stop layers during etching.
Innovation Solution
Implementing an ultrathin barrier layer with a thickness of 6 nm or less, formed using conformal atomic layer deposition, between the bottom electrode and the bottom electric contact to reduce step height and improve uniformity of the dielectric etch stop layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick barrier layer is used, then material diffusion prevention is improved, but processing time increases and fabrication cost increases
Solution Approach 1:
The patent changes the thickness parameter of the barrier layer from conventional thick (e.g., 10-20 nm) to ultrathin (e.g., 1-5 nm), and modifies the material composition to achieve equivalent or superior diffusion barrier performance at reduced thickness, thereby decreasing processing time while maintaining reliability
Solution Approach 2:
The patent employs composite barrier layer structures combining multiple materials (e.g., titanium nitride and tungsten nitride, or aluminum oxide and silicon oxide) to achieve enhanced diffusion prevention with reduced overall thickness, resolving the contradiction between barrier effectiveness and processing efficiency
2Reliability
If a thick barrier layer is used, then material diffusion prevention is improved, but fabrication cost increases
Solution Approach 1:
By reducing barrier layer thickness from conventional to ultrathin dimensions and optimizing material composition, the patent decreases material consumption and deposition costs while maintaining or improving barrier effectiveness, thereby reducing fabrication cost
Solution Approach 2:
The patent applies different materials or thicknesses at different locations within the barrier layer structure, optimizing performance where needed while reducing material usage in less critical areas, thus lowering overall fabrication cost
3Reliability
If a thick barrier layer is used, then diffusion barrier performance is improved, but step height increases
Solution Approach 1:
The patent reduces the thickness parameter of the barrier layer to ultrathin dimensions (e.g., 1-5 nm versus conventional 10-20 nm), directly decreasing step height while compensating for reduced barrier performance through material composition optimization and conformal deposition techniques
4Reliability
If a thick barrier layer is used, then diffusion barrier performance is improved, but thickness uniformity worsens
Solution Approach 1:
The patent reduces barrier layer thickness to ultrathin dimensions where conformal deposition techniques can achieve superior thickness uniformity and control, eliminating the accumulation of deposition variations that plague thicker layers, thereby improving manufacturing precision
Solution Approach 2:
The patent employs periodic pulsed deposition processes with intermediate annealing or plasma treatment steps to ensure uniform thickness and composition throughout the ultrathin barrier layer, achieving both diffusion barrier performance and thickness uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ultrathin barrier layer reduces step height by 15% or more, enhances dielectric etch stop layer uniformity, and improves manufacturability, resulting in lower costs, higher yields, and facilitated integration of resistive memory devices in advanced technology nodes.
Implementation Method 1
a barrier layer located between the bottom electrode and the bottom electric contact to the memory device. The barrier layer may prevent diffusion of material of the metal feature into the bottom electrode
Implementation Method 2
formed using conformal atomic layer deposition
Data Source
AI summary
A resistive memory device includes an ultrathin barrier layer disposed between the bottom electrode and the bottom electric contact to the memory device. The ultrathin barrier layer may reduce the overall step height of the resistive memory elements by 15% or more, including up to about 20% or more. The use of an ultrathin barrier layer may additionally improve the uniformity of the thickness of the dielectric etch stop layer that partially underlies and extends between the memory elements by at least about 15%. The use of an ultrathin barrier layer may result in improved manufacturability and provide reduced costs and higher yields for resistive memory devices, and may facilitate integration of resistive memory devices in advanced technology nodes.