In-Memory Bayesian Neural Networks for Uncertainty Estimation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Traditional implementations of Bayesian neural networks are inefficient in generating Gaussian random variables and performing high-dimensional integrals, limiting their effectiveness in mission-critical systems that require accurate uncertainty estimation.

Innovation Solution

Implementing a Bayesian neural network in a memory device using memory cells and stochastic pulse generators, which enables efficient creation of Gaussian random variables and parallel processing of high-dimensional integrals, leveraging the hardware of the memory device to improve computational efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional implementations of Bayesian neural networks are used, then the system can perform uncertainty estimation, but the computational efficiency is poor due to inefficiency in generating Gaussian random variables and performing high-dimensional integrals

Engineering Contradiction:
Improveuncertainty estimation accuracyVSAvoidcomputational efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent replaces traditional software-based Bayesian neural network computations with a hardware-based memory device implementation. The memory device uses stochastic pulse generators to physically generate Gaussian random variables and performs high-dimensional integrals through parallel hardware operations, substituting the mechanical/software computation system with a dedicated hardware system that achieves both accuracy and efficiency.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If Bayesian neural networks are implemented in memory devices, then computational efficiency improves through parallel processing, but the device complexity increases

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidmemory device structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory device is designed to perform multiple functions: it serves as both traditional memory storage and as a computational engine for Bayesian neural networks. The same memory cells and pulse generators used for data storage are also utilized for generating Gaussian random variables and performing high-dimensional integrals, allowing one device to fulfill multiple roles without proportionally increasing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11681906B2Bayesian network in memory
Publication Date: 2023.06.20 MICRON TECHNOLOGY INC
  • US11681906B2 patent drawing
  • US11681906B2 patent drawing
  • US11681906B2 patent drawing

AI summary

Apparatuses and methods can be related to implementing a Bayesian neural network in a memory. A Bayesian neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be programed and used to store weights of the Bayesian neural network and perform operations consistent with the Bayesian neural network.