Multi-Channel Memory BER Balancing for Throughput Bottlenecks

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Solution Overview

Problem

Multi-channel flash memory devices face throughput imbalances due to varying bit error rates (BER) across different memory dies, leading to overall performance being constrained by the 'slowest' die, which can be costly to address with complex hardware arbiters.

Innovation Solution

Incorporating a BER estimator and throughput balancer within the controller to dynamically adjust clock rates, buffer allocations, and sense/transfer command execution times based on estimated BERs, allowing for balanced throughput without adding complex hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple memory dies are included to enhance data storage capacity, then storage density is improved, but throughput is limited by the slowest die with highest BER

Engineering Contradiction:

Improvestorage capacityVSAvoidthroughput

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The patent implements dynamic adjustment of operating parameters (clock rates, buffer allocations, sense/transfer command execution times) for each memory die based on their individual BER characteristics. This allows the system to adaptively optimize throughput by balancing the performance of multiple dies rather than being constrained by the slowest one, directly resolving the contradiction between storing more data and maintaining high throughput.

Inventive Principle:

Principle #15Dynamics

2Productivity

If complex hardware arbiters are added to balance throughput across dies, then throughput performance is improved, but device complexity increases

Engineering Contradiction:

ImprovethroughputVSAvoidhardware complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces complex hardware arbitration mechanisms with a controller-based software/firmware solution that estimates BER and dynamically adjusts operating parameters. This substitution achieves throughput balancing without adding complex hardware arbiters, resolving the contradiction between improving throughput and maintaining simplicity.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes operating parameters (clock rates, buffer allocations, command execution times) based on BER estimates to balance throughput across dies. This parameter-based approach avoids the need for complex hardware arbitration while achieving the desired throughput performance, directly addressing the contradiction between throughput improvement and device complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20180173655A1Multi-channel memory operations based on bit error rates

Publication Date: 2018.06.21 SANDISK TECHNOLOGIES LLC

AI summary

In an illustrative example, a device includes a memory and a controller that is coupled to the memory and that is configured to communicate with the memory using at least a first channel and a second channel. The controller includes a bit error rate (BER) estimator configured to estimate a first BER corresponding to the first channel and a second BER corresponding to the second channel. The controller also includes a throughput balancer configured to determine whether to adjust at least one of a first clock rate of the first channel or a second clock rate of the second channel based on the first BER and the second BER.