Memory Device Bias Block for Erase Voltage Transfer
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Solution Overview
Problem
Memory devices with three-dimensionally arranged memory cells face challenges in reducing their area footprint, particularly due to the need for multiple driver circuits to charge bit lines and source lines for efficient hole injection during data erasing.
Innovation Solution
The introduction of a bias block that is not used for data storage but assists in data erasing by receiving and transferring erase voltages to select gate lines, word lines, and source lines, eliminating the need for individual driver circuits for each bit line, thereby reducing the overall device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple driver circuits are provided for each bit line to charge bit lines and source lines for efficient hole injection during data erasing, then data erasing efficiency is improved, but device area increases
Solution Approach 1:
The bit line serves multiple functions: it acts as both a data access line for reading/writing operations and as a source line for hole injection during erase operations. This multi-functionality eliminates the need for separate driver circuits dedicated solely to erase operations, thereby reducing device area while maintaining erase efficiency
Solution Approach 2:
The patent merges the bit line and source line functions by applying the same voltage to the bit line during erase operations. This consolidation allows a single driver circuit to perform both data access and hole injection functions, reducing the total number of driver circuits needed and thus decreasing device area
2Quantity of substance
If three-dimensional arrangement of memory cells is implemented, then storage density is improved, but device area reduction is hindered by additional driver circuits
Solution Approach 1:
The patent transitions from two-dimensional to three-dimensional memory cell arrangement, stacking memory cells vertically to increase storage density. The innovative use of bit lines for dual purposes (data access and hole injection) compensates for the increased complexity by reducing the footprint of control circuits, allowing the 3D structure to achieve area reduction despite higher integration
3Manufacturing precision
If individual driver circuits are provided for each bit line, then control precision for hole injection is improved, but device complexity increases
Solution Approach 1:
The bit line is designed to serve dual functions: data access during read/write operations and hole injection during erase operations. This universal design maintains control precision by using the same line for both purposes while significantly reducing device complexity by eliminating separate driver circuits for hole injection
Data Source
AI summary
Each of first, second, and third string has one end coupled to a first interconnect and another end coupled to a second interconnect. The first, second, and the third strings include first, second, and third memory cell transistor, respectively. A first power supply line is coupled to a gate of the first memory cell transistor via a first transistor and coupled to a gate of the second memory cell transistor via a second transistor. A second power supply line is coupled to a gate of the third memory cell transistor and applies a voltage different from that of the first power supply line during data erasing.