Memory Bias Mode Switching for Cache Coherency Control
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Solution Overview
Problem
Existing electronic devices face challenges in managing cache coherency when multiple processors share data, leading to inefficiencies and the need for improved methods to support independent operations while maintaining data consistency.
Innovation Solution
An operating method for electronic devices that includes bias modes to manage cache coherency, allowing processors to operate independently by partially blocking coherency during certain operations and recovering it when necessary, using a coherency host and accelerators to maintain, block, and recover memory coherency as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherency is maintained between multiple processors, then data consistency is improved, but operation independence and performance are worsened
Solution Approach 1:
The patent implements dynamic switching between two bias modes (first and second bias modes) that control the level of cache coherency intervention. The system can transition between these modes based on operational requirements, allowing cache coherency to be enabled when data consistency is needed and disabled when independent operation is required, thus resolving the contradiction between reliability and productivity
Solution Approach 2:
The system changes the parameter of cache coherency control by switching between different bias modes. In the first bias mode, the processor intervenes in cache coherency operations, while in the second bias mode, the processor does not intervene, allowing independent operations. This parameter change enables the system to adapt between data consistency and operation independence requirements
2Reliability
If cache coherency control is implemented, then data consistency is improved, but time consumption and resource usage are worsened
Solution Approach 1:
The patent applies partial action by selectively enabling cache coherency control only when necessary. Instead of continuously maintaining cache coherency, the system uses the first bias mode to intervene in cache coherency operations only during specific periods, and uses the second bias mode to allow independent operations without coherency overhead, thus reducing time consumption and resource usage while maintaining data consistency when needed
Data Source
AI summary
An operating method of an electronic device which includes a processor and a memory, the method including: accessing, using the processor, the memory without control of an external host device in a first bias mode; sending, from the processor, information of the memory to the external host device when the first bias mode ends; and accessing, using the processor, the memory under control of the external host device in a second bias mode.