Memory Bias Current Sensing for Faster Data Line Settling
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Solution Overview
Problem
The increasing resistance in data lines of memory devices with stacked memory cells leads to a significant decrease in data line current, resulting in prolonged settling times during sensing operations, which slows down read and program verification operations, thereby reducing the overall performance of the memory device.
Innovation Solution
A dedicated memory block is controlled by a memory controller to drive a pillar current and generate a sensing current, combining it with the pillar current to form a total data line current, which is sensed by a sense amplifier, thereby increasing the data line current and reducing settling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically to increase storage capacity, then storage density is improved, but data line resistance increases causing slower sensing operations
Solution Approach 1:
The data line is segmented into multiple sections with intermediate sensing points. Instead of sensing the entire data line current at one endpoint, the current is sensed at multiple locations along the data line path, reducing the effective resistance each sensing operation must overcome and enabling faster read operations in vertically stacked memory structures
Solution Approach 2:
Intermediate sensing circuits are introduced as mediators between the memory cells and the main data line. These intermediate sensors detect current at multiple points along the data line, effectively reducing the impact of total line resistance and enabling faster sensing operations without compromising storage capacity
2Loss of time
If data line current is increased to reduce settling time, then sensing speed is improved, but power consumption increases
Solution Approach 1:
Instead of increasing current throughout the entire data line system, the patent applies partial action by introducing intermediate sensing points that require less current to achieve the same sensing speed. This reduces the overall power consumption while still achieving fast settling times at the critical sensing locations
Solution Approach 2:
Intermediate sensing circuits act as mediators that enable fast sensing with reduced current requirements. By detecting current at multiple intermediate points rather than relying on high current at a single endpoint, the system achieves fast settling times with lower overall power consumption
3Loss of time
If data line resistance is reduced to improve sensing speed, then settling time is reduced, but device complexity increases
Solution Approach 1:
The data line is segmented into multiple sections with intermediate sensing points. This segmentation approach reduces settling time by creating shorter effective sensing paths without requiring physical modification of the data line resistance, thereby achieving fast sensing with minimal increase in device complexity
Solution Approach 2:
Intermediate sensing circuits are introduced as mediators that enable fast sensing operations without requiring reduction of data line resistance. This approach achieves reduced settling times while avoiding the complexity associated with physically modifying data line characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased data line current improves the sensing speed of memory cells, enhancing the performance of memory devices with multiple stacked levels.
Implementation Method 1
a total data line current, which is sensed by a sense amplifier
Data Source
AI summary
Methods, systems, and devices for techniques for faster sensing operation are provided. In one embodiment, a memory device comprises a data line; a plurality of memory blocks coupled to the data line; and a dedicated memory block coupled to the data line. The dedicated memory block is controllable to generate a sensing current. The memory device further comprises a memory controller configured to, during sensing of a selected memory block of the plurality of memory blocks, cause one or more regulators to: drive the selected memory block such that a pillar current flows through a pillar of the selected memory block, and drive the dedicated memory block to generate the sensing current. The memory device further comprises a sense amplifier configured to sense a data line current. The data line current is a combination of the pillar current and the sensing current.