3D Memory Bit-Line-Bias Block Using GIDL Dummy NAND Strings
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Solution Overview
Problem
Existing three-dimensional semiconductor devices require high voltage transistors for bit-line biasing during erase operations, which increases the area requirement for sense amplifier/bit-line-bias circuits.
Innovation Solution
The introduction of a bit-line-bias vertical transistor block, which includes a two-dimensional array of dummy NAND strings, allows for the elimination of high voltage transistors by using gate induced drain leakage (GIDL) hole currents to bias the bit lines during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage transistors are used for bit-line biasing during erase operations, then the erase operation can be performed, but the area requirement for sense amplifier/bit-line-bias circuits increases
Solution Approach 1:
The patent extracts the high voltage transistor functionality from the sense amplifier/bit-line-bias circuit by introducing a separate bit-line-bias block. This block contains dummy NAND strings with select gates that can be independently controlled to generate the necessary bit-line bias voltage during erase operations, thereby removing the area burden from the main sense amplifier circuit.
Solution Approach 2:
The patent segments the memory device into functional blocks: data storage memory blocks and a dedicated bit-line-bias block. The bit-line-bias block is further segmented into multiple dummy NAND strings, each with its own select gates. This segmentation allows independent control of bias generation without affecting the main storage functionality, resolving the area contradiction.
2Power
If high voltage transistors are used for bit-line biasing, then bit-line bias voltage can be generated, but device complexity increases
Solution Approach 1:
The dummy NAND strings in the bit-line-bias block serve multiple functions: they generate bit-line bias voltage during erase operations, and their select gates can be controlled to route voltages as needed. This multi-functionality eliminates the need for separate high voltage transistor circuits, reducing overall device complexity while maintaining power generation capability.
Solution Approach 2:
The bit-line-bias block uses its own internal dummy NAND string structure and select gates to generate and regulate the bit-line bias voltage without requiring external high voltage transistors or complex bias generation circuits. The structure is self-sufficient, reducing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the area requirement for sense amplifier/bit-line-bias circuits, increases memory device density, and enables efficient erase operations without the need for high voltage transistors.
Implementation Method 1
allows for the elimination of high voltage transistors by using gate induced drain leakage (GIDL) hole currents to bias the bit lines during erase operations
Data Source
AI summary
A semiconductor device includes a plurality of memory blocks and a bit-line-bias block. A source-drain erase bias voltage is applied between a source line and a bit lines through the bit-line-bias block during an erase operation.