Semiconductor Memory Bias Segmentation for Leakage and Reliability
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining operating reliability under diverse conditions and environments due to limitations in controlling bias voltages, particularly for vertically stacked transistors, which require complex fabrication and result in performance degradation and increased power consumption.
Innovation Solution
The semiconductor memory device employs a structure where the memory cell area and peripheral circuit area are stacked and overlapped, allowing for independent control of different bias voltages applied to first and second transistors, optimizing threshold voltages and reducing leakage currents through adaptive bias adjustment based on temperature and operational states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked transistors are used in memory cell area, then integration density is improved, but fabrication complexity increases and performance degrades
Solution Approach 1:
The device is segmented into two distinct areas: memory cell area with vertically stacked first transistors and peripheral circuit area with planar second transistors. This segmentation allows each area to be optimized independently - the memory cell area achieves high integration density through vertical stacking while the peripheral circuit area maintains ease of fabrication through planar structures.
Solution Approach 2:
Different transistor structures are applied to different locations based on functional requirements. The memory cell area uses vertically stacked transistors for high density, while the peripheral circuit area uses planar transistors for easier fabrication and better performance, creating local optimization throughout the device.
2Quantity of substance
If vertically stacked transistors are used, then integration density is improved, but transistor performance deteriorates
Solution Approach 1:
The device separates vertically stacked transistors in the memory cell area from planar transistors in the peripheral circuit area. This segmentation allows planar transistors to handle performance-critical operations while vertically stacked transistors provide high-density storage, balancing integration density with transistor performance.
3Reliability
If different bias voltages are applied to memory cell and peripheral circuit transistors, then operating reliability is improved, but device complexity increases
Solution Approach 1:
The device structure is segmented into two areas with independently controllable bias voltages. The memory cell area receives first bias voltage while the peripheral circuit area receives second bias voltage, allowing independent optimization of each area's operating characteristics without requiring complex inter-area coordination.
Solution Approach 2:
Different bias voltages are applied to different locations based on their specific operational requirements. The memory cell transistors receive bias optimized for storage operations while peripheral circuit transistors receive bias optimized for processing operations, achieving local optimization throughout the device.
Data Source
AI summary
A semiconductor memory device is provided which is capable of adaptively controlling bias and a method of operating the same. The semiconductor memory device includes: a memory cell area including a plurality of first transistors to which a first bias voltage is applied; and a peripheral circuit area which overlaps the memory cell area in a first direction and includes a plurality of second transistors to which a second bias voltage controlled differently from the first bias voltage is applied.