Memory Read Error Handling Using Bin-Based Corrective Reads

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Solution Overview

Problem

Existing memory sub-systems face performance degradation due to slow charge loss (SCL) leading to increased read error rates and latency, particularly in memory cells with longer data retention, as conventional read error handling (REH) flows are not optimized for varying cell states.

Innovation Solution

Implementing bin-based read error handling (REH) flows with a fast corrective read (CR) operation tailored to the classification of memory cells, using different REH flows based on bin classification to mitigate temporal voltage shift (TVS) and reduce latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional read error handling flows are used for all memory cells, then read error handling is performed uniformly, but latency increases and performance degrades due to slow charge loss in cells with longer data retention

Engineering Contradiction:
Improveread error handlingVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments memory cells into different bins based on their data retention characteristics and temporal voltage shift profiles. By dividing the memory cell population into distinct groups (bins) with similar characteristics, the system can apply tailored read error handling flows to each bin, avoiding the latency penalty of uniform conservative handling across all cells.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic selection of read error handling flows based on the bin classification of memory cells. The system adapts the error handling approach in real-time by selecting appropriate flows according to the specific retention characteristics of each cell bin, optimizing latency while maintaining reliability.

Inventive Principle:
Principle #15Dynamics

2Loss of time

If optimized fast corrective read operations are applied to all memory cells, then latency is reduced, but read error rates increase due to insufficient error handling for cells with longer data retention

Engineering Contradiction:
ImprovelatencyVSAvoidread error rate
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent applies different quality levels of error handling to different memory cell bins. Cells in bins with shorter data retention receive faster, less conservative error handling, while cells in bins with longer retention receive more robust error handling. This local differentiation optimizes overall system performance by matching error handling intensity to actual cell characteristics.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameters of read error handling operations based on bin classification. Different read error handling flows with varying parameters (such as read voltage levels, retry counts, and correction algorithms) are applied to different bins, allowing the system to optimize latency for cells that need it while maintaining reliability for cells that require more protection.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If bin-based read error handling flows are implemented, then read error handling is optimized for varying cell states, but device complexity increases

Engineering Contradiction:
Improveread error handling performanceVSAvoidread error handling structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

While segmentation into bins increases complexity, it enables the system to manage complexity through organization. By grouping cells with similar characteristics into bins, the system reduces the complexity of managing individual cell variations and enables more efficient error handling strategies.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates multiple read error handling flows that can be universally applied to different bins. Each flow is designed to handle specific characteristics of memory cell bins, and the same set of flows can be reused across different bin types, reducing the overall complexity compared to creating custom handling logic for each individual cell or bin combination.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260023645A1Bin-based read error handling flows using a fast corrective read operation
Publication Date: 2026.01.22 MICRON TECHNOLOGY INC
  • US20260023645A1 patent drawing
  • US20260023645A1 patent drawing
  • US20260023645A1 patent drawing

AI summary

A system comprises a memory device and a processing device, operatively coupled with the memory device. The processing device detects an error during a read operation on a set of target cells of the memory device. The processing device selects, based on a state information bin with which the set of target cells is associated, a read error handling (REH) flow for the set of target cells, wherein the set of target cells is associated with the state information bin based on corresponding cell state information. The processing device executes the REH flow on the set of target cells of the memory device to correct the error.