Semiconductor Memory BISS Circuit for Faster Wafer-Level Defect Testing
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Solution Overview
Problem
The complexity of semiconductor memory devices with high capacity and integration requires lengthy testing times, which decreases productivity and increases costs, especially during traditional burn-in processes that can damage equipment due to excessive current consumption.
Innovation Solution
A built-in self-stress (BISS) test circuit is implemented at the wafer-level to perform multi-pattern tests, reducing the need for external equipment and allowing for defect detection similar to traditional burn-in tests without the risk of equipment damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a typical ATE testing method is used to access and test semiconductor memory devices from the outside, then comprehensive testing can be performed, but it takes a long time and decreases productivity
Solution Approach 1:
The patent implements a built-in self-test (BIST) circuit within the semiconductor memory device that enables the device to test itself autonomously. The BIST circuit generates test patterns internally and evaluates the memory device's operation without requiring external ATE equipment, thereby dramatically reducing test time while maintaining comprehensive testing coverage.
Solution Approach 2:
The BIST circuit performs testing operations in advance during the manufacturing process before the device is packaged and shipped. By conducting comprehensive tests preliminarily at the wafer level or before final assembly, the need for lengthy post-packaging ATE testing is eliminated, improving productivity while ensuring device quality.
2Reliability
If a TDBI process is used to apply stress and perform write operations for defect detection, then defects can be identified, but excessive current consumption can melt package balls and damage test equipment
Solution Approach 1:
The BIST circuit performs stress testing and write operations at reduced current levels compared to the excessive current used in TDBI processes. By applying partial stress that is sufficient for defect detection but controlled to avoid overheating, the method achieves reliable defect identification without melting package balls or damaging test equipment.
Solution Approach 2:
The BIST circuit acts as an intermediary that mediates between the need for comprehensive stress testing and the risk of equipment damage. It controls the test current and operation parameters to provide adequate stress for defect detection while preventing the excessive current conditions that cause package ball melting and equipment damage in traditional TDBI processes.
3Productivity
If multiple word lines are simultaneously enabled through one-time active command to increase test speed, then productivity improves, but it becomes difficult to control and test the device
Solution Approach 1:
The BIST circuit incorporates feedback mechanisms that automatically control and monitor the enabling of multiple word lines during testing. The circuit receives feedback from the memory device's response and dynamically adjusts the test procedure, making it easy to manage simultaneous word line operations without increasing procedural complexity. This feedback control enables high-speed testing with multiple enabled word lines while maintaining simple, automated test sequences.
Data Source
AI summary
Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.