Memory BIST Address Transition Routing for Full Coverage
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Solution Overview
Problem
Memory devices face a significant challenge in minimizing transition time between addresses during built-in self-test (BIST) due to the large number of memory cells, often requiring only a subset to be tested, which may not accurately represent the entire array's functionality.
Innovation Solution
Implementing a greedy routing strategy that uses the minimum number of address transitions to exercise all decoder line transitions, ensuring all possible faults are exposed in the shortest execution time by selecting candidate transitions with the shortest distance from the current location and recording transitions to avoid duplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory cells are tested individually, then testing completeness is improved, but test time becomes prohibitively long
Solution Approach 1:
The patent segments the memory array testing into two phases: a first phase that tests a subset of memory cells using conventional methods, and a second phase that tests remaining cells using optimized address transition patterns. This segmentation allows comprehensive testing while reducing overall test time by applying different testing strategies to different portions of the memory array.
Solution Approach 2:
The patent performs preliminary testing of a subset of memory cells before testing the remaining cells. By completing the first phase of testing with a representative subset, the system establishes baseline reliability metrics that guide the second phase testing, ensuring comprehensive coverage while minimizing total test time.
2Loss of time
If a subset of memory cells is tested, then test time is reduced, but testing accuracy represents the entire array
Solution Approach 1:
The patent applies partial action by testing a carefully selected subset of memory cells in the first phase, then extends testing to remaining cells in the second phase. The subset is designed to be representative of the entire array, providing sufficient accuracy for reliability assessment while significantly reducing test time compared to testing all cells individually.
Solution Approach 2:
The patent uses feedback from the first phase testing results to guide the second phase testing strategy. By analyzing which memory cells were tested and their performance, the system optimizes the remaining test sequence to maximize information gain while minimizing additional test time, ensuring accurate representation of the entire memory array.
3Loss of time
If address transitions are minimized, then execution time is reduced, but coverage of all addresses may be incomplete
Solution Approach 1:
The patent dynamically adjusts the address transition sequence based on the current location in the memory array. By optimizing the transition path at each step to visit untested addresses with minimum transitions, the system achieves complete address coverage while minimizing total execution time. The testing sequence adapts to the current state to ensure efficient coverage.
Solution Approach 2:
The patent changes the testing parameters by switching from conventional individual cell testing to optimized address transition-based testing. By modifying the test sequence parameters to prioritize address transitions and use dynamic routing strategies, the system achieves complete coverage with reduced execution time compared to traditional methods.
Data Source
AI summary
Transitioning to all addresses of a memory array during BIST includes arranging the addresses as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array. A column of a selected current location can correspond to a destination address of a memory transition. The destination addresses can identify a candidate row of the matrix which corresponds to the destination address. The candidate row can be different from a row of the current location. A next location can be determined that has not been recorded in the candidate row that has a minimum column distance from the column of the first location as compared to other locations that have not been recorded in the candidate row.