Memory Control Circuit BIST Arbitration for Multi-Channel Latency
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Solution Overview
Problem
Existing multi-channel memory testing methods are inefficient due to varying access latencies across channels, making it challenging to perform low-cost, fast, and accurate tests in hand-held smart mobile devices and computers.
Innovation Solution
A memory control circuit with a built-in self-test (BIST) circuit and channel controllers that arbitrates and selects channel controllers based on completed test commands, sending next test commands dynamically to optimize test efficiency across multiple channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multi-channel memory testing is performed using conventional methods, then test coverage is achieved, but test time is extended due to varying access latencies across channels
Solution Approach 1:
The BIST controller dynamically adjusts the testing process by receiving completion information from channel controllers and selectively sending next test commands based on real-time channel status. This dynamic adaptation allows the system to handle varying access latencies without extending test time, while maintaining test accuracy through proper synchronization.
Solution Approach 2:
The system implements feedback mechanisms where channel controllers send completion information back to the BIST controller. This feedback loop enables the BIST controller to make informed decisions about command scheduling, ensuring that tests are completed efficiently across all channels while maintaining accuracy through proper timing and synchronization.
2Productivity
If a simple BIST circuit is used for memory testing, then test cost is reduced, but test efficiency decreases due to inability to handle multiple channels optimally
Solution Approach 1:
The BIST controller is designed with multi-functionality to handle multiple channel controllers simultaneously. It can receive completion information from any channel, arbitrate between competing channels, and send next test commands to appropriate channels based on their specific needs. This universal design improves test efficiency without requiring separate BIST circuits for each channel.
Solution Approach 2:
The BIST controller acts as an intermediary between multiple channel controllers and the memory channels. It coordinates the testing process by receiving completion status from channels, making arbitration decisions, and distributing next commands appropriately. This mediator role enables efficient multi-channel testing while keeping the overall system architecture manageable.
3Measurement precision
If channel controllers operate independently without coordination, then channel autonomy is maintained, but test synchronization becomes difficult due to access latency variations
Solution Approach 1:
Channel controllers send completion information feedback to the BIST controller, enabling precise synchronization. The BIST controller uses this feedback to determine when each channel is ready for the next command, ensuring accurate timing despite varying access latencies. This feedback mechanism maintains test synchronization while preserving channel independence.
Solution Approach 2:
The BIST controller prepares and queues next test commands in advance based on expected channel completion times. By anticipating which channels will be ready next and preparing appropriate commands, the system achieves precise synchronization without requiring complex real-time coordination between channels during test execution.
Data Source
AI summary
A memory control circuit, coupled to a multi-channel memory, includes a plurality of channel controllers coupled to respective channel memories of the multi-channel memory, and a built-in self-test (BIST) circuit. The BIST circuit includes a BIST controller and a plurality of command index registers which store respective command indexes related to the channel controllers. The BIST controller receives notification from at least two channel controllers of the channel controllers, which indicates that the at least two channel controllers complete respective current test commands. When the BIST controller arbitrates, the BIST controller selects at least a channel controller from the at least two channel controllers which send the notification, and sends respective next test command(s) to the selected at least one channel controller based on the respective command index(es) of the selected at least one channel controller.