Memory Array BIST Diagnostics for Real-Time Column Fail Analysis
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Solution Overview
Problem
Conventional built-in self-test circuitry for memory arrays struggles to accurately and efficiently determine the type and extent of column failures, requiring additional debugging and slowing down the testing process.
Innovation Solution
Integrated circuit devices with enhanced built-in self-test diagnostic circuitry, including a fail counter circuit and a diagnostic column fail circuit, capable of determining the number of failing addresses and cells, and distinguishing between local and global column fails during testing without stopping the test operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional built-in self-test circuitry is used to test memory arrays, then the testing process can be performed, but the ability to accurately determine column failure types is insufficient and additional debugging is required
Solution Approach 1:
The memory array is divided into multiple subarrays, and the diagnostic circuitry is segmented to independently analyze failure patterns in each subarray. The diagnostic column fail circuit examines failure distributions across different subarrays to distinguish between local and global column failures, enabling accurate failure type identification without requiring overly complex testing infrastructure.
Solution Approach 2:
The built-in self-test circuitry incorporates diagnostic capabilities that enable the memory array to self-diagnose column failure types. The fail counter circuit and diagnostic column fail circuit work together to automatically determine whether column failures are local or global without requiring external debugging equipment, thereby improving measurement precision while maintaining reasonable device complexity.
2Measurement precision
If conventional testing approaches are used, then basic memory testing can be performed, but test coverage is limited and detailed failure statistics are not available
Solution Approach 1:
The diagnostic column fail circuit operates continuously during the built-in self-test operation without requiring interruptions. The circuit continuously monitors and counts failures in real-time, maintaining test coverage and generating detailed failure statistics concurrently with the memory testing process, thereby improving measurement precision while preserving testing productivity.
Solution Approach 2:
The fail counter circuit provides real-time feedback on failure counts and patterns during the testing operation. This feedback mechanism enables the diagnostic circuitry to accumulate detailed failure statistics continuously, providing comprehensive test coverage information without slowing down the testing process, as the feedback is integrated into the ongoing test cycles.
3Measurement precision
If the testing operation is stopped to analyze column failures, then accurate failure analysis can be performed, but the testing process is slowed down
Solution Approach 1:
The diagnostic column fail circuit performs failure analysis continuously during the testing operation without requiring the test to be stopped. The circuit maintains real-time monitoring of column failures across subarrays, enabling accurate failure analysis to proceed concurrently with the memory testing cycles, thereby improving measurement precision while minimizing time loss.
Solution Approach 2:
The fail counter circuit preliminarily counts and categorizes failures during the testing operation, preparing failure statistics in advance. This preliminary action allows accurate failure analysis to be performed during normal testing rather than requiring post-test analysis or test interruptions, thereby improving measurement precision while reducing the time loss that would result from stopping the testing operation.
Data Source
AI summary
Integrated circuit devices and methods of operation are provided which include a memory array having an array of memory cells arranged in rows and columns, and circuitry operatively couple to the memory array. In one aspect, the circuitry includes a fail counter circuit, and the circuitry is configured to facilitate preforming a testing operation on the memory array, with the fail counter circuit being operable during the testing operation in a selected one of a plurality of fail counter modes. The plurality of fail counter modes include an address fail counter mode to determine a number of failing addresses of the memory array during the testing operation, and a cell fail counter mode to determine the number of failing memory cells of the memory array during the testing operation. In another aspect, the circuitry includes a diagnostic column fail circuit to determine a type of column fail.