Memory BIST Circuit Address Segmentation for Decoder Fault Testing
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Solution Overview
Problem
Current integrated circuit memory testing methods are inefficient in thoroughly checking for array faults and address decoder faults, particularly when using built-in self-testing (BIST) circuitry, leading to potential missed decoder faults and prolonged testing times.
Innovation Solution
A single-step testing approach is implemented using increased address space, which includes generating multiple address signals to select different parts of the circuit, employing comparators to check for faults, and utilizing multiplexers to switch between functional and test modes, enabling comprehensive testing of array and decoder faults within the BIST circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire memory is tested with redundancy enabled using traditional multi-step approaches, then decoder faults can be detected, but the testing time becomes prohibitively long
Solution Approach 1:
The patent segments the address space into multiple regions, each associated with different redundancy configurations. By dividing the testing into targeted segments rather than exhaustive full-memory testing, the approach achieves comprehensive decoder fault detection while significantly reducing overall test time.
Solution Approach 2:
The patent performs preliminary testing of the memory array without enabling redundancy before activating redundancy for decoder fault detection. This preliminary action identifies array faults early, allowing the test procedure to focus subsequent redundant-based testing only where decoder faults are suspected, thereby reducing total testing time.
2Productivity
If redundancy address pin is set to 0 to speed up testing, then test time is reduced, but decoder faults are missed
Solution Approach 1:
The patent dynamically configures the redundancy address pin settings based on the specific testing phase and objectives. Rather than statically setting the redundancy address pin to 0 for speed, the system adapts the redundancy configuration to match the current test requirements, ensuring both speed and comprehensive fault detection.
Solution Approach 2:
The patent changes the redundancy address parameter during different phases of testing. By modifying the redundancy address pin settings from fixed values to variable values that correspond to different address space segments, the system maintains high test speed while ensuring all decoder faults are detected through targeted redundancy activation.
3Device complexity
If traditional BIST algorithms are used without increased address space, then testing is simpler, but array faults and decoder faults are not thoroughly checked
Solution Approach 1:
The patent extends the address space dimension by utilizing redundancy address pins in combination with regular address lines. This dimensional expansion of the address space allows the BIST algorithm to access and test decoder circuits that would otherwise be inaccessible, achieving thorough fault detection without significantly increasing algorithmic complexity.
Data Source
AI summary
A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.