Memory Built-In Self-Test Circuitry with Dual Access Paths
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Solution Overview
Problem
Existing circuitry testing techniques face challenges in effectively testing memory error protection circuitry, such as ECC and parity checking circuitry, especially in online modes where testing must occur without disrupting the operation of the circuitry under test.
Innovation Solution
The implementation of memory built-in self-test circuitry with both indirect and direct access paths, allowing for the generation and verification of error protection codes while bypassing error protection circuitry, and detecting fault conditions through fault detection circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If online testing is performed through the error protection circuitry, then the testing can be conducted without interrupting normal operations, but it becomes difficult to distinguish between faults in the memory circuitry and faults in the error protection circuitry
Solution Approach 1:
The access circuitry is segmented into two distinct paths: an indirect access path that goes through the error protection circuitry and a direct access path that bypasses it. This segmentation allows the MBIST circuitry to independently test memory through both paths, enabling differentiation between memory faults and error protection circuitry faults while maintaining online operation capability.
2Productivity
If direct access path is used for testing, then the testing speed is improved, but the error protection circuitry cannot be tested
Solution Approach 1:
The access circuitry dynamically switches between direct and indirect access paths based on the specific testing objective. The MBIST circuitry can select the direct path for high-speed memory testing and the indirect path for error protection circuitry verification, allowing both testing speed and comprehensive fault detection to be achieved through adaptive path selection.
3Reliability
If indirect access path is used for testing, then the error protection circuitry can be tested, but the testing process becomes slower
Solution Approach 1:
The testing system performs partial testing through the indirect path (only when error protection circuitry verification is needed) rather than requiring all tests to go through the slower indirect path. This allows the system to maintain high overall testing productivity by using the direct path for most memory tests while still achieving comprehensive error protection circuitry verification when necessary.
Data Source
AI summary
Apparatus comprises memory circuitry having a plurality of addressable memory entries storing respective data items and associated error protection codes; memory error protection circuitry to generate the error protection code for a data item stored to the memory circuitry, the error protection code for a given data item stored to the memory circuitry depending upon at least the given data item and a memory address defining a memory entry to which the given data item is stored, and to perform a check operation to check for consistency between a retrieved data item, the memory address defining a memory entry from which the given data item is retrieved and the error protection code associated with the retrieved data item; memory built-in self-test circuitry to test the memory and memory error protection circuitry; and access circuitry to provide an indirect access path between the memory built-in self-test circuitry a memory which accesses the memory circuitry via the memory error protection circuitry and a direct access path between the memory built-in self-test circuitry and a memory entry which bypasses the memory error protection circuitry; the memory built-in self-test circuitry being configured to execute a test operation by writing a test value to a first memory entry of the memory circuitry having a first test memory address via the indirect access path; retrieving the test value and associated error protection code from the first memory entry by the direct access path; writing the retrieved test value and associated error protection code to a second memory entry having a second test memory address via the direct access path, there being a difference in at least one bit between the first test memory address and the second test memory address; and retrieving the test value and associated error protection code from the second memory entry via the indirect access path; the memory built-in self-test circuitry comprising fault detection circuitry configured to detect a fault condition when the result of the check operation performed by the memory error protection circuitry is inconsistent with the difference between the first test memory address and the second test memory address.